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US 2006/0220265 A1Published application
Alignment mark for semiconductor device, and semiconductor device
AssigneeSeiko Epson Corporation
InventorsTakafumi Noda, Hiroshi Fukuda
Life of this patent
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Abstract
An alignment mark for a semiconductor device is provided. The alignment mark defines a plane pattern and includes a conductive layer embedded in a recessed section provided in an insulation layer, and an oxidation barrier layer provided on the conductive layer, wherein an area occupancy ratio of the recessed section in the plane pattern is 5% or greater.
Claims6
An alignment mark for a semiconductor device, the alignment mark defining a plane pattern, the alignment mark comprising:
- a conductive layer embedded in a recessed section provided in an insulation layer;
- and
- an oxidation barrier layer provided on the conductive layer,
- wherein an area occupancy ratio of the recessed section in the plane pattern is 5% or greater.
1 more element
Dependencies are inferred from the claim text.