Analytic structure for failure analysis of semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-Hyun Lee, Hun-Seong Choi
Life of this patent
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Abstract
An analytic structure includes a plurality of analytic fields formed on a predetermined region of a semiconductor substrate; semiconductor transistors arranged in the analytic fields to compose an array structure, each transistor having a gate electrode and an impurity region; wordlines arranged crosswise on the analytic fields and connecting the semiconductor transistors; and bitline structures connecting the impurity regions of the semiconductor transistors lengthwise, each bitline structure having a bitline and a vertical interconnection structure connecting the bitline with the impurity region. The bitlines have different heights according to their positions on the analytic fields.
Claims8
An analytic structure for failure analysis of a semiconductor device, comprising:
- a plurality of analytic fields formed on a predetermined region of a semiconductor substrate;
- semiconductor transistors arranged in the analytic fields to compose an array structure, each transistor having a gate electrode and an impurity region;
- wordlines arranged crosswise on the analytic fields and connecting the semiconductor transistors;
- and
- bitline structures connecting the impurity regions of the semiconductor transistors lengthwise, each bitline structure having a bitline and a vertical interconnection structure connecting the bitline with the impurity region,
- wherein the bitlines have different heights according to their positions on the analytic fields.
Dependencies are inferred from the claim text.