US 2006/0220230 A1 · Semiconductor device and method of manufacturing thereof

Abstract

In order to implement a high-density high-performance semiconductor system small in size, there is provided a method for implementing three-dimensional connection between a plurality of semiconductor chips differing from each other with the shortest metal interconnect length, using penetration electrodes, thereby enabling a fast operation at a low noise level, the method being a three-dimensional connection method very low in cost, and short in TAT in comparison with the known example, capable of bonding at an ordinary temperature, and excellent in connection reliability. For example, in a three-dimensional chip laminate structure with a metal interconnect substrate for effecting connection between upper and lower semiconductor chips, disposed in between the upper and lower chips differing from each other, through-holes reaching respective electrodes on the surface layer side are formed on the respective backside face sides of the semiconductor chip and the metal interconnect substrate, a metal plating film is applied to the sidewalls of the respective through-holes and peripheries thereof, on the backside face side, and metal bumps of the semiconductor chip stacked on the upper tier side are pressed into contact with the interiors of the respective through-holes with the metal plated film applied thereto to be thereby inserted therein, due to portions of the respective metal bumps, undergoing deformation, causing the metal bumps to be geometrically caulked inside the respective through-holes formed in the semiconductor chip and the metal interconnect substrate, thereby implementing electrical connection.

Claims10

Dependent claims

A method of manufacturing a semiconductor device, comprising the steps of:

preparing a semiconductor chip provided with bumps;
preparing an organic metal interconnect substrate having through-holes, an electrode being formed along the respective inner wall faces of the through-holes;
and
pressing the bump into contact with the respective through-holes to be inserted therein, due to deformation of the bump, accompanied by plastic flow.

1 more element

A semiconductor device having a structure comprising:

a first metal interconnect substrate;
a first semiconductor chip mounted over the first metal interconnect substrate;
a second metal interconnect substrate;
a second semiconductor chip different from the first semiconductor chip, mounted over the second metal interconnect substrate, wherein the second semiconductor chip is stacked over the first metal interconnect substrate through the intermediary of the second metal interconnect substrate,
the first metal interconnect substrate having a main face and a backside face, on respective sides thereof, opposite from each other;
first electrodes disposed on the main face;
a bump disposed on top of the respective first electrode, protruding from the main face;
through-holes each extending from the backside face toward the main face;
and
second electrodes formed along the respective inner wall faces of the through-holes, electrically connected to the first electrodes, respectively, via an interconnect layer formed on the main face,
the first semiconductor chip having a main face and a backside face, on respective sides thereof, opposite from each other;
first electrodes disposed on the main face;
through-holes each reaching the respective first electrodes from the backside face;
and
second electrodes formed along the respective inner wall faces of the through-holes, electrically connected to the first electrodes, respectively,
the second semiconductor chip having a main face and a backside face, on respective sides thereof, opposite from each other;
first electrodes disposed on the main face;
and
a bump disposed on top of the respective first electrode, protruding from the main face;
the second metal interconnect substrate having a main face and a backside face, on respective sides thereof, opposite from each other;
first electrodes disposed on the main face;
a bump disposed on top of the respective first electrode, protruding from the main face;
through-holes each extending from the backside face toward the main face;
and
second electrodes formed along the respective inner wall faces of the through-holes, electrically connected to the first electrodes, respectively, via an interconnect layer formed on the main face;
a portion of each of bumps of the first semiconductor chip being pressed into contact with the respective through-holes of the first metal interconnect substrate to be thereby inserted therein through the intermediary of the second electrodes of the first metal interconnect substrate, due to the portion undergoing deformation accompanied by plastic flow, thereby causing the bumps to be electrically connected to the first electrodes of the first metal interconnect substrate, respectively,
a portion of each of the bumps of the second semiconductor chip being pressed into contact with the respective through-holes of the second metal interconnect substrate to be thereby inserted therein through the intermediary of the second electrodes of the second metal interconnect substrate, due to the portion undergoing deformation accompanied by plastic flow, thereby causing the bumps to be electrically connected to the first electrodes of the second metal interconnect substrate, respectively, and
a portion of each of the bumps of the second metal interconnect substrate being pressed into contact with the respective through-holes of the first semiconductor chip to be thereby inserted therein through the intermediary of the second electrodes of the first semiconductor chip, due to the portion undergoing deformation accompanied by plastic flow, thereby causing the bumps to be electrically connected to the first electrodes of the first semiconductor chip, respectively.

25 more elements

A semiconductor device having a structure comprising:

a first metal interconnect substrate;
a first semiconductor chip mounted over the first metal interconnect substrate;
second metal interconnect substrates;
second semiconductor chips each different from the first semiconductor chip, mounted over each of the second metal interconnect substrates, wherein the second semiconductor chips are stacked over the first metal interconnect substrate through the intermediary of the respective second metal interconnect substrates,
the first metal interconnect substrate having:
a main face and a backside face, on respective sides thereof, opposite from each other;
first electrodes disposed on the main face;
a bump disposed on top of the respective first electrode, protruding from the main face;
through-holes each extending from the backside face toward the main face;
and
second electrodes formed along the respective inner wall faces of the through-holes, electrically connected to the first electrodes, respectively, via an interconnect layer formed on the main face, the first semiconductor chip having:
a main face and a backside face, on respective sides thereof, opposite from each other;
first electrodes disposed on the main face;
through-holes each reaching the respective first electrodes from the backside face;
and
second electrodes formed along the respective inner wall faces of the through-holes, electrically connected to the first electrodes, respectively,
the respective second semiconductor chips, except the second semiconductor chip in the uppermost tier, having:
a main face and a backside face, on respective sides thereof, opposite from each other;
first electrodes disposed on the main face;
through-holes each reaching the respective first electrodes from the backside face;
and
second electrodes formed along the respective inner wall faces of the through-holes, electrically connected to the first electrodes, respectively,
the second metal interconnect substrates each having:
a main face and a backside face, on respective sides thereof, opposite from each other;
first electrodes disposed on the main face;
a bump disposed on top of the respective first electrode, protruding from the main face;
through-holes each extending from the backside face toward the main face;
and
second electrodes formed along the respective inner wall faces of the through-holes, electrically connected to the first electrodes, respectively, via an interconnect layer formed on the main face;
a portion of each of bumps of the first semiconductor chip being pressed into contact with the respective through-holes of the first metal interconnect substrate to be thereby inserted therein through the intermediary of the second electrodes of the first metal interconnect substrate, due to the portion undergoing deformation accompanied by plastic flow, thereby causing the bumps to be electrically connected to the first electrodes of the first metal interconnect substrate, respectively,
a portion of each of bumps of the respective second semiconductor chips being pressed into contact with each of the through-holes of the respective second semiconductor chips and the second metal interconnect substrate to be thereby inserted therein through the intermediary of the second electrodes of the respective second semiconductor chips and the respective second metal interconnect substrate, due to the portion undergoing deformation accompanied by plastic flow, thereby causing the bumps to be electrically connected to the first electrodes of the plurality of the second semiconductor chips and second metal interconnect substrate, respectively, and
a portion of each of the bumps of the respective second metal interconnect substrates being pressed into contact with the respective through-holes of the first semiconductor chip to be thereby inserted therein through the intermediary of the second electrodes of the first semiconductor chip, due to the portion undergoing deformation accompanied by plastic flow, thereby causing the bumps to be electrically connected to the first electrodes of the first semiconductor chip, respectively.

29 more elements

A semiconductor device having a structure comprising:

a metal interconnect substrate;
a semiconductor chip mounted over the metal interconnect substrate, wherein a plurality of the semiconductor chips are stacked one on top of another over the semiconductor chip mounted over the metal interconnect substrate through the intermediary of each of other metal interconnect substrates differing from the metal interconnect substrate over which the semiconductor chip are mounted,
the metal interconnect substrate having:
a main face and a backside face, on respective sides thereof, opposite from each other;
first electrodes disposed on the main face;
a bump disposed on top of the respective first electrode, protruding from the main face;
through-holes each extending from the backside face toward the main face;
and
second electrodes formed along the respective inner wall faces of the through-holes, electrically connected to the first electrodes, respectively, via an interconnect layer formed on the main face,
the semiconductor chip having:
a main face and a backside face, on respective sides thereof, opposite from each other;
first electrodes disposed on the main face;
and
a bump disposed on top of the respective first electrode, protruding from the main face;
a portion of each of the bumps of the semiconductor chip being pressed into contact with the respective through-holes of the metal interconnect substrate to be thereby inserted therein through the intermediary of the second electrodes of the metal interconnect substrate, due to the portion undergoing deformation accompanied by plastic flow, thereby causing the bumps to be electrically connected to the first electrodes of the metal interconnect substrate, respectively, and
a portion of each of the bumps of the metal interconnect substrate being pressed into contact with the respective through-holes of the metal interconnect substrate to be thereby inserted therein through the intermediary of the second electrodes of the other semiconductor chip, due to the portion undergoing deformation accompanied by plastic flow, thereby causing the bumps to be electrically connected to the first electrodes of the other semiconductor chip, respectively.

13 more elements

Dependencies are inferred from the claim text.

Semiconductor device and method of manufacturing thereof

Life of this patent

Semiconductor device and method of manufacturing thereof

Life of this patent

Abstract

Claims10