Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

A semiconductor chip comprising:

• an internal circuit formed on a semiconductor substrate;
• an interlayer insulating layer formed on the semiconductor substrate having the internal circuit;
• at least one internal power line and at least one internal ground line formed on and/or in the interlayer insulating layer, the at least one internal power line and the at least one internal ground line being electrically connected to a power terminal and a ground terminal of the internal circuit, respectively;
• a power chip pad and a ground chip pad formed on the interlayer insulating layer, the power chip pad and the ground chip pad being electrically connected to the internal power line and the internal ground line, respectively;
• a passivation layer formed over the internal power line, the internal ground line, the power chip pad, and the ground chip pad;
• a redistributed power line formed over the passivation layer, the redistributed power line directly connecting the internal power line to the power chip pad through a power via-hole and a power chip pad opening, respectively, which penetrate at least the passivation layer;
• and
• a redistributed ground line formed over the passivation layer, the redistributed ground line directly connecting the internal ground line to the ground chip pad through a ground via-hole and a ground chip pad opening, respectively, which penetrate at least the passivation layer.

A semiconductor chip comprising:

• an internal circuit formed on a semiconductor substrate;
• an interlayer insulating layer formed over the internal circuit;
• first and second internal power supply lines formed on and/or in the interlayer insulating layer, and electrically connected to first and second power supply terminals of the internal circuit, respectively;
• first and second power supply chip pads formed on the interlayer insulating layer, and electrically connected to the first and second internal power supply lines, respectively;
• a passivation layer and a first lower dielectric layer sequentially stacked over the first and second internal power supply lines and the first and second power supply chip pads;
• a first redistributed power supply line disposed on the first lower dielectric layer, the first redistributed power supply line directly connecting the first internal power supply line to the first power supply chip pad through a first via-hole and a first power supply chip pad opening, respectively, which penetrate at least the first lower dielectric layer and the passivation layer;
• a first upper dielectric layer formed over the first redistributed power supply line;
• and
• a second redistributed power supply line disposed on the first upper dielectric layer, the second redistributed power supply line directly connecting the second internal power supply line to the second power supply chip pad through a second via-hole and a second power supply chip pad opening, respectively, which penetrate at least the first upper and lower dielectric layers and the passivation layer.

A method of fabricating a semiconductor chip, the method comprising:

• forming an internal circuit on a semiconductor substrate;
• forming an internal interconnection electrically connected to the internal circuit;
• forming a chip pad electrically connected to the internal interconnection over the internal circuit;
• forming a passivation layer over the internal interconnection and the chip pad, the passivation layer having a via-hole and a chip pad opening that expose the internal interconnection and the chip pad, respectively;
• and
• forming a redistributed metal interconnection on the passivation layer, the redistributed metal interconnection being directly connected to the internal interconnection and the chip pad through the via-hole and the chip pad opening, respectively.

A semiconductor chip comprising:

• an internal circuit formed on a semiconductor substrate;
• a chip pad and an internal interconnection each formed on the semiconductor substrate, the chip pad electrically connected to the internal circuit through the internal interconnection;
• a passivation layer covering the substrate, the chip pad and the internal interconnection;
• and
• a redistributed metal interconnection extending over the passivation layer and also over the chip pad and the internal interconnection,
• wherein the redistributed metal interconnection couples the internal interconnection with the chip pad through a via-hole and a chip pad opening, respectively, which penetrates the passivation layer.