Method for forming an improved isolation junction in high voltage LDMOS structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYou-Kuo Wu, Edward Chiang
Life of this patent
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Abstract
A method for forming an improved isolation junction in an LDMOS structure to reduce current leakage at high operating Voltages including forming doped regions in a buried layer prior to forming an overlying epitaxial region including doped isolation regions followed by a drive-in process to form a continuous isolation region by intermixing the doped regions formed in the buried layer with the overlying doped isolation regions.
Claims32
A method for forming an improved isolation junction in an LDMOS structure comprising the steps of:
- providing a semiconductor substrate comprising a first conductivity;
- forming a first doped region comprising a second conductivity extending a first thickness from the semiconductor substrate surface;
- forming a second doped region comprising the second conductivity within the first doped region at a higher doping density compared to the first doped region;
- forming an epitaxial semiconductor layer comprising a first conductivity over and contacting the first and second doped regions;
- forming a third doped region comprising the second conductivity within the epitaxial semiconductor layer overlying the second doped region extending a second thickness from the epitaxial semiconductor layer surface;
- and,
- carrying out at least one thermal treatment to intermix the second and third doped regions.
A method for forming an improved isolation junction in an LDNMOS structure comprising the steps of:
- providing a semiconductor substrate comprising P-type conductivity;
- forming a first doped region comprising N-type conductivity extending a first thickness from a portion of the semiconductor substrate surface;
- forming a second doped region comprising N-type conductivity within a portion of the first doped region at a thickness less than the first thickness and at a higher doping density compared to the first doped region;
- forming an epitaxial semiconductor layer comprising P-type conductivity type over and contacting the first and second doped regions:
- forming a third doped region comprising N-type conductivity within the epitaxial semiconductor layer overlying the second doped region to extend through a portion of the epitaxial semiconductor layer surface to leave a P-type conductivity portion of the epitaxial semiconductor layer overlying the second doped region;
- and,
- carrying out at least one annealing process to intermix the second and third doped regions to form a continuous N-type conductivity isolation region penetrating the epitaxial semiconductor layer.
The method of claim 20, wherein the third doped region comprises isolation regions in a high voltage laterally diffused NMOS (LDNMOS) device formed adjacent to respective P-well and N-well doped channel regions underlying a gate structure.
An LDMOS structure having an improved isolation junction comprising:
- a semiconductor substrate comprising a first conductivity type;
- a first doped region comprising a second conductivity type extending a first thickness from the semiconductor substrate surface;
- a second doped region comprising the second conductivity type within the first doped region comprising the second conductivity type within the first doped region at a higher doping density compared to the first doped region;
- a epitaxial semiconductor layer comprising a first conductivity type over and contacting the first and second doped regions;
- a third doped region comprising the second conductivity type within the epitaxial semiconductor layer overlying the second doped region extending a second thickness from the epitaxial semiconductor layer surface;
- wherein the second and third doped regions form a continuous doped region comprising the second conductivity type extending through the epitaxial semiconductor layer thickness.
An LDMOS structure having an improved isolation junction comprising:
- a semiconductor substrate comprising P-type conductivity;
- a first doped region comprising N-type conductivity extending a first thickness from a portion of the semiconductor substrate surface;
- a second doped region comprising N-type conductivity within a portion of the first doped region at a thickness less than the first thickness and at a higher doping density compared to the first doped region;
- an epitaxial semiconductor layer comprising P-type conductivity over and contacting the first and second doped regions;
- wherein a third doped region comprising N-type conductivity is disposed within the epitaxial semiconductor layer overlying the second doped region to extend through a portion of the epitaxial semiconductor layer surface to form a continuous N-type conductivity isolation region penetrating the epitaxial semiconductor layer.
Dependencies are inferred from the claim text.