US 2006/0220170 A1Published application

High-voltage field effect transistor having isolation structure

OwnerChih-Feng Huang, Tuo-Hsin Chien +2inventors

InventorsChih-Feng Huang, Tuo-Hsin Chien, Jenn-yu Lin, Ta-yung Yang

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Abstract

A high-voltage MOSFET having isolation structure is provided. An N-type MOSFET includes a first deep N-type well. A first P-type region is formed in the first deep N-type well to enclose a first source region and a first contact region. A first drain region is formed in the first deep N-type well. A P-type MOSFET includes a second deep N-type well. A second P-type region is formed in the second deep N-type well to enclose a second drain region. A second source region and a second contact region are formed in the second deep N-type well. A polysilicon gate oxidation layer is disposed above the thin gate oxidation layer and the thick field oxidation layer to control the current in the channel of the MOSFET. Separated P-type regions provide further isolation between MOSFETs. A first gap and a second gap increase the breakdown voltage of the high-voltage MOSFET.

Claims6

Dependent claims

A high-voltage N-type MOSFET, comprising:

a P-type substrate;
a first N-type diffusion region, having N-type conductive ions to form a first deep N-type well in said P-type substrate;
a first P-type diffusion region, having P-type conductive ions to form a first P-type region in said first deep N-type well;
a first drain diffusion region, having N+-type conductive ions to form a first drain region in said first N-type diffusion region;
a first source diffusion region, having N+-type conductive ions to form a first source region, wherein a first channel is formed between said first source region and said first drain region;
a first contact diffusion region, having P+-type conductive ions to form a first contact region, wherein said first P-type region encloses said first source region and said first contact region;
a plurality of separated P-type diffusion regions, having P-type conductive ions to form a plurality of P-type separated regions in said P-type substrate to provide isolation;
a first thin gate oxidation layer and a first thick field oxidation layer, formed on said P-type substrate;
a first polysilicon gate, located on said first thin gate oxidation layer and said first thick field oxidation layer to control a current flow in said first channel;
a silicon oxide isolation layer, covering said first polysilicon gate and said first thick field oxidation layer;
a first drain metal contact, having a first metal electrode, connected with said first drain diffusion region;
a first source metal contact, having a second metal electrode, connected with said first contact diffusion region and said first source diffusion region;
and
a first gap between said first thick field oxidation layer and said first P-type region, maintaining a space for increasing a breakdown voltage of said high-voltage N-type MOSFET.

11 more elements

A high-voltage P-type MOSFET, comprising:

a P-type substrate;
a second N-type diffusion region, having N-type conductive ions to form a second deep N-type well in said P-type substrate;
a second P-type diffusion region, having P-type conductive ions to form a second P-type region in said second deep N-type well;
a second drain diffusion region, having P+-type conductive ions to form a second drain region in said second P-type diffusion region;
a second source diffusion region, having P+-type conductive ions to form a second source region, wherein a second channel is formed between said second source region and said second drain region;
a second contact diffusion region, having N+-type conductive ions to form a second contact region, wherein said second N-type diffusion region encloses said second source region and said second contact region;
a plurality of separated P-type diffusion regions, having P-type conductive ions to form a plurality of P-type separated regions in said P-type substrate to provide isolation;
a second thin gate oxidation layer and a second thick field oxidation layer, formed on said P-type substrate;
a second polysilicon gate located on said second thin gate oxidation layer and said second thick field oxidation layer to control a current flow in said second channel;
a silicon oxidation isolation layer, covering said second polysilicon gate and said second thick field oxidation layer;
a second drain metal contact, having a third metal electrode connected with said second drain diffusion region;
a second source metal contact, having a fourth metal electrode connected with said second contact diffusion region and said second source diffusion region;
and
a second gap between said second thick field oxidation layer and said second deep N-type well, maintaining a space for increasing a breakdown voltage of said high-voltage P-type MOSFET.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/096,959Filed 31 Mar 2005
Published: 5 Oct 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/0281
Of double-diffused metal oxide semiconductor [DMOS] FETs: of lateral dmos [ldmos] fets
H10D 30/65
Double-diffused metal-oxide semiconductor [DMOS] FETs: lateral dmos [ldmos] fets
H10D 84/013
The components including insulated gates, e.g. IGFETs: manufacturing their source or drain regions, e.g. silicided source or drain regions