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US 2006/0220168 A1Published application
Shielding high voltage integrated circuits
AssigneeMonolithic Power Systems, Inc.
InventorMichael Hsing
Life of this patent
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Abstract
Methods and apparatus are disclosed for protecting the electric field distribution of the high voltage semiconductor devices and of the high voltage junction terminating structures from the influences of overlaying interconnections. The proposed methods and apparatus prevent the breakdown voltage of the devices from decreasing. At the same time, circuit areas are reduced and parasitic resistances inherent to the conventional approach are eliminated or minimized.
Claims20
A high voltage integrated circuit (HVIC) comprising:
- means for driving a gate of a high voltage transistor;
- means for controlling the gate driving means;
- means for shifting up a signal voltage when the signal is transmitted from the control means to the gate driving means;
- and
- means for shifting down a signal voltage when the signal is transmitted from the gate driving means to the control means, wherein:
- the gate driving means is substantially enclosed by a high voltage junction terminating (HVJT) structure of a loop geometry;
- the shifting up means is located outside the HVJT loop and is not exclusively surrounded by any part of the HVJT loop or exclusively surrounded by any other HVJT structure;
- and
- the shifting down means is located inside the HVJT loop structure and is not exclusively surrounded by any part of the HVJT loop or exclusively surrounded by any other HVJT structure.
6 more elements
A high voltage integrated circuit (HVIC) comprising:
- at least one high-side gate drive (HSGD) unit for driving a gate of a high voltage transistor;
- a control unit (CU) for controlling the at least one HSGD unit based on I/O signals to the HVIC;
- and
- a level shifter unit (LSU) acting as an interface between the CU and the HSGD for shifting up a signal voltage when the signal is transmitted from the CU to the HSGD, and for shifting down a signal voltage when the signal is transmitted from the HSGD to the CU, wherein:
- the HSGD is surrounded by a high voltage junction terminating (HVJT) loop structure;
- the shifting up of the signal voltage is performed by a MOS (metal-oxide semiconductor) or a MIS (metal-insulator semiconductor) of a first channel type that is located outside the HVJT loop structure and is not exclusively surrounded by a part of the HVJT loop or exclusively surrounded by another HVJT structure;
- and
- the shifting down of the signal voltage is performed by a MOS or a MIS of a second channel type that is located inside the HVJT loop structure and is not exclusively surrounded by a part of the HVJT loop or exclusively surrounded by another HVJT structure.
5 more elements
A high voltage gate driving apparatus comprising:
- at least one high voltage gate drive unit for driving a gate of a high voltage transistor;
- a high voltage junction terminating (HVJT) loop structure surrounding the high voltage gate drive unit;
- a MOS (metal-oxide semiconductor) or a MIS (metal-insulator semiconductor) FET transistor of a first channel type for shifting up a signal voltage that enters into the HVJT loop, wherein the transistor is located outside the HVJT loop structure and is not exclusively surrounded by any part of the HVJT loop or exclusively surrounded by another HVJT structure;
- and
- a MOS or MIS FET transistor of a second channel type for shifting down a signal voltage that exits out of the HVJT loop, wherein the transistor is located inside the HVJT loop structure and is not exclusively surrounded by any part of the HVJT loop or exclusively surrounded by another HVJT structure.
2 more elements
A method of driving a gate of a high voltage transistor, the method comprising:
- electrically isolating a semiconductor area for generating gate driving signals, wherein the area is isolated by a high voltage junction terminating (HVJT) structure that surrounds the area;
- transmitting gate driving control signals into the isolated area from a first voltage level shifter situated outside the isolated area, wherein the first voltage level shifter increases the signal voltage;
- and
- transmitting gate drive control signals out of the isolated area from a second voltage level shifter situated inside the isolated area, wherein the second voltage level shifter decreases the signal voltage, and wherein:
- the shifting up of the signal voltage is performed by a MOS (metal-oxide semiconductor) or a MIS (metal-insulator semiconductor) of a first channel type that is located outside the HVJT loop structure and is not exclusively surrounded by a part of the HVJT loop or exclusively surrounded by another HVJT structure;
- and
- the shifting down of the signal voltage is performed by a MOS or a MIS of a second channel type that is located inside the HVJT loop structure and is not exclusively surrounded by a part of the HVJT loop or exclusively surrounded by another HVJT structure.
4 more elements
Dependencies are inferred from the claim text.