MOSFET structure with ultra-low K spacer

A field effect transistor comprising:

• a substrate comprising source/drain extensions positioned laterally adjacent a channel region;
• a gate oxide layer on said channel region and overlapping portions of said source/drain extensions;
• a gate conductor on said gate oxide layer and comprising a sidewall;
• and
• a sidewall spacer positioned laterally adjacent said sidewall and on a corresponding one of said source/drain extensions;
• wherein said sidewall spacer comprises:
• a first dielectric layer comprising a vertical portion positioned adjacent said sidewall and a horizontal portion positioned above said corresponding source/drain extension;
• and
• a second dielectric layer positioned adjacent said vertical portion and above said horizontal portion,
• wherein said first dielectric layer has a permittivity value of less than three.

A method of forming a field effect transistor, said method comprising:

• forming a gate oxide layer and a gate conductor on a channel region and overlapping a source/drain extension;
• forming a sacrificial layer adjacent a sidewall of said gate conductor and above said source/drain extension;
• forming a permeable low-K dielectric layer adjacent said sacrificial layer and above said source/drain extension;
• and
• heating said sacrificial layer;
• wherein said sacrificial layer volatizes into molecules during said heating process and wherein said molecules diffuse through said permeable low-K dielectric layer, thereby, forming a gap.

A method of forming a field effect transistor, said method comprising:

• forming a gate oxide layer and a gate conductor on a channel region and overlapping a source/drain extension;
• forming a first dielectric layer comprising a vertical portion positioned adjacent a sidewall of said gate conductor and a horizontal portion positioned above said source/drain extension;
• and
• forming a second dielectric layer positioned adjacent said vertical portion and above said horizontal portion,
• wherein said first dielectric layer has a permittivity value of less than three.