Semiconductor device and its manufacture method
AssigneeFujitsu Limited
InventorsToru Anezaki, Jusuke Ogura, Taiji Ema
Life of this patent
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Abstract
A semiconductor device includes: a semiconductor substrate; and STIs formed in the semiconductor substrate and defining a high voltage transistor area and a low voltage transistor area, the STIs including: a first STI with a first liner including a thermal oxide film and not including a nitride film and surrounding at least a portion of the high voltage transistor area; and a second STI with a second liner of a lamination of a thermal oxide film and a nitride film and surrounding the low voltage transistor area.
Claims14
A semiconductor device comprising:
- a semiconductor substrate;
- and
- STIs formed in said semiconductor substrate and defining a high voltage transistor area and a low voltage transistor area, said STIs including:
- a first STI with a first liner including a thermal oxide film and not including a nitride film and surrounding at least a portion of said high voltage transistor area;
- and a second STI with a second liner of a lamination of a thermal oxide film and a nitride film and surrounding said low voltage transistor area.
A semiconductor device comprising:
- a semiconductor substrate;
- and
- STIs formed in said semiconductor substrate and defining a high voltage transistor area and a low voltage transistor area, said STIs including:
- a first STI with a first liner including a lamination of a thermal oxide film and a nitride film and surrounding at least a portion of said high voltage transistor area;
- and a second STI with a second liner of a lamination of a thermal oxide film and a nitride film and surrounding said low voltage transistor area,
- wherein the thermal oxide film of said first liner is thicker than the thermal oxide film of said second liner, and a radius of curvature in a vertical cross section in at least part of said high voltage transistor area is larger than a radius of curvature in a vertical cross section in said low voltage transistor area.
A semiconductor device manufacture method comprising the steps of:
- (a) etching a semiconductor substrate having a high voltage transistor area and a low voltage transistor area to form a first isolation trench surrounding said high voltage transistor area, by using a first hard mask and a resist pattern formed by first photolithography;
- (b) thermally oxidizing a surface of said first isolation trench;
- (c) etching said semiconductor substrate to form a second isolation trench surrounding said low voltage transistor area, by using a second hard mask and a resist pattern formed by second photolithography;
- (d) after said step (c), thermally oxidizing surfaces of said first and second isolation trenches;
- and
- (e) after said step (d), forming a nitride film liner in said first and second isolation trenches.
A semiconductor device manufacture method comprising the steps of:
- (a) etching a semiconductor substrate having a high voltage transistor area and a low voltage transistor area to form isolation trenches by using a hard mask and a resist pattern formed by photolithography;
- (b) thermally oxidizing surfaces of said isolation trenches;
- (c) after said step (b), depositing a nitride film in said isolation trenches;
- and
- (d) after said step (c), removing the nitride film in said isolation trench in said high voltage transistor area.
Dependencies are inferred from the claim text.