Semiconductor device and manufacturing method thereof
AssigneeFujitsu Limited
InventorNaoyoshi Tamura
Life of this patent
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Abstract
The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure.
Claims19
A semiconductor device comprising:
- an element isolation structure in which trenches formed in an element isolation region on a semiconductor substrate are filled up with insulating materials;
- a first conductivity type element formed in a first active region divided by said element isolation structure;
- and
- a second conductivity type element formed in a second active region divided by said element isolation structure,
- said element isolation structure comprising:
- a first element isolation region of said element isolation region including regions adjacent to a pair of opposed ends of said second active region, said first element isolation region being filled with an insulating material that gives a compressive stress to said second active region;
- and
- a second element isolation region of said element isolation region other than said first element isolation region, said second element isolation region being filled with an insulating material that gives a tensile stress to each of said first and second active regions.
A manufacturing method of a semiconductor device in which first and second active regions are divided by an element isolation structure formed in an element isolation region on a semiconductor substrate, and first and second conductivity type elements are formed in said first and second active regions, respectively,
- said element isolation region comprising a first element isolation region including regions adjacent to a pair of opposed ends of said second active region, and a second element isolation region other than said first element isolation region,
- said method comprising the steps of:
- forming a first trench in said second element isolation region on said semiconductor substrate, and filling up said first trench with an insulating material that gives a tensile stress to each of said first and second active regions;
- and
- forming a second trench in said first element isolation region on said semiconductor substrate, and filling up said second trench with an insulating material that gives a compressive stress to said second active region.
A manufacturing method of a semiconductor device in which first and second active regions are divided by an element isolation structure formed in an element isolation region on a semiconductor substrate, and first and second conductivity type elements are formed in said first and second active regions, respectively,
- said element isolation region comprising a first element isolation region including regions adjacent to a pair of opposed ends of said second active region, and a second element isolation region other than said first element isolation region,
- said method comprising the steps of:
- forming a first trench in said element isolation region on said semiconductor substrate, and filling up said first trench with an insulating material that gives a tensile stress to each of said first and second active regions;
- and
- forming a second trench in a portion of said insulating material having filled up said first trench to give a tensile stress, corresponding to said first element isolation region, and filling up said second trench with an insulating material that gives a compressive stress to said second active region.
Dependencies are inferred from the claim text.