Low contact resistance cmos circuits and methods for their fabrication
AssigneeAdvanced Micro Devices, Inc.
InventorPaul Besser
Life of this patent
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Abstract
A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer.
Claims20
A CMOS integrated circuit including an NMOS transistor having N-type source and drain regions and a PMOS transistor having P-type source and drain regions, the CMOS integrated circuit comprising:
- a first metal silicide contacting the N-type source and drain regions;
- a second metal silicide different than the first metal silicide contacting the P-type source and drain regions;
- a first transition metal contacting the first metal silicide;
- a second transition metal different than the first barrier metal contacting the second metal silicide;
- a first metal plug electrically contacting the first transition metal;
- and
- a second metal plug electrically contacting the second transition metal.
A method for fabricating a CMOS integrated circuit having an N-type drain region and a P-type drain region, the method comprising the steps of:
- depositing a high barrier height silicide forming metal in contact with the P-type drain region;
- heating the high barrier height silicide forming metal to form a high barrier height metal silicide in contact with the P-type drain region;
- depositing a low barrier height silicide forming metal in contact with the N-type drain region;
- heating the low barrier height silicide forming metal to form a low barrier height metal silicide in contact with the N-type drain region;
- depositing and patterning a dielectric layer to form a first opening exposing a portion of the high barrier height metal silicide and a second opening exposing a portion of the low barrier height metal silicide;
- depositing a low barrier height metal into the second opening and contacting the portion of the low barrier height metal silicide;
- depositing a high barrier height metal into the first opening and contacting the portion of the high barrier height metal silicide;
- depositing a conductive capping layer in contact with the high barrier height metal and in contact with the low barrier height metal;
- and
- filling the first opening and the second opening with a plug metal in contact with the conductive capping layer.
A CMOS integrated circuit having an N-type drain region and a P-type drain region comprising:
- a first plug comprising a first stack of conductive layers electrically coupled to the N-type drain region;
- and
- a second plug comprising a second stack of conductive layers different than the first stack electrically coupled to the P-type drain region.
A CMOS integrated circuit having first N-type region and a second P-type region comprising:
- a first transition metal electrically coupled to the first N-type region;
- a second transition metal different than the first transition metal electrically coupled to the second P-type region;
- a conductive barrier layer overlying each of the first transition metal and the second transition metal;
- and
- a plug metal overlying the conductive barrier layer.
Dependencies are inferred from the claim text.