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US 2006/0220140 A1Published application
Method of forming an integrated power device and structure
AssigneeSemiconductor Components Industries, LLC
InventorsFrancine Robb, Stephan Robb, Prasad Venkatraman, Zia Hossain
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Abstract
In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
Claims20
An integrated power device comprising:
- a semiconductor substrate of a first conductivity type having a first surface;
- an epitaxial layer on the first surface of the semiconductor substrate, the epitaxial layer having a first surface that is opposite to the first surface of the semiconductor substrate;
- a vertical power transistor formed on the first surface of the epitaxial layer, the vertical power transistor having a channel region;
- and
- a first doped region having the first conductivity type and within the epitaxial layer, the first doped region underlying at least a portion of the vertical power transistor wherein the first doped region does not extend to the first surface of the epitaxial layer.
2 more elements
A method of forming an integrated power device comprising:
- providing a semiconductor substrate of a first conductivity type having a surface;
- forming a semiconductor layer on the surface of the semiconductor substrate;
- forming a vertical transistor on a first surface of the semiconductor layer;
- and
- forming a first doped region of the first conductivity type within the semiconductor layer and underlying a channel region of the vertical transistor.
2 more elements
Dependencies are inferred from the claim text.