CMOS SRAM cells employing multiple-gate transistors and methods fabricating the same

A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell, comprising:

• a pair of cross-coupled CMOS inverters having active regions disposed in a vertically-stacked and fin-shaped pattern of single crystal semiconductor regions of opposite conductivity type;
• a first access transistor having a current carrying terminal electrically connected to gate terminals of a first one of the pair of cross-coupled CMOS inverters;
• and
• a second access transistor having a current carrying terminal electrically connected to gate terminals of a second one of the pair of cross-coupled CMOS inverters.

A complementary metal oxide semiconductor static random access memory (CMOS SRAM) cell, comprising:

• a semiconductor substrate;
• a fin body protruded from the semiconductor substrate;
• a first multiple-gate field effect transistor (FET) including a first insulated common gate electrode surrounding the fin body, and first upper and lower source/drain regions spaced apart from each other and disposed in the fin body;
• a second multiple-gate FET including a second insulated common gate electrode surrounding the fin body, and second upper and lower source/drain regions spaced apart from each other and disposed in the fin body;
• a first interconnection electrically connecting the first insulated common gate electrode to the second upper and lower drain regions;
• and
• a second interconnection electrically connecting the second insulated common gate electrode to the first upper and lower drain regions.