Fin-type channel transistor and method of manufacturing the same

A method of manufacturing a Fin-type channel transistor comprising:

• forming a Fin portion in a rectangular solid shape by patterning a semiconductor layer formed on a substrate;
• forming a gate insulating film on a pair of first side portions of the Fin portion, the first side portions being opposed to each other;
• forming a gate electrode at least on the first side portions of the Fin portion so that the gate insulating film is sandwiched between the gate electrode and the Fin portion;
• and
• depositing an insulating material on an entire surface, etching the insulating material and the Fin portion to expose a pair of second side portions of the Fin portion, the second side portions being opposed to each other and extending in a direction substantially perpendicular to the pair of first side portions of the Fin portion, the semiconductor layer being left at both sides of the gate electrode so as to connect to bottom portions of the second side portions.

A method of manufacturing a Fin-type channel transistor comprising:

• forming a first insulating layer on a semiconductor layer formed on a substrate;
• forming a Fin portion in a rectangular solid shape by patterning the semiconductor layer;
• forming a gate insulating film on a pair of first side portions of the semiconductor layer, the first side portions being opposed to each other;
• forming a gate electrode material film on an entire surface, and then forming a second insulating layer on the gate electrode material film;
• patterning the second insulating layer and the gate electrode material film to form a gate electrode covering the gate insulating film formed on the first side portions of the semiconductor layer and the first insulating layer on the semiconductor layer, the second insulating layer being left on the gate electrode;
• depositing an insulating material on an entire surface, etching the insulating material and the Fin portion to expose a pair of second side portions of the semiconductor layer and to form gate sidewalls of the insulating material on the second insulating layer patterned and side portions of the gate electrode, the second side portions being opposed to each other and extending in a direction substantially perpendicular to the pair of first side portions of the semiconductor layer, and the semiconductor layer being left at both sides of the gate electrode so as to connect to bottom portions of the second side portions;
• forming first impurity regions in the second side portions exposed and forming a second impurity region in the semiconductor layer left;
• removing the second insulating layer sandwiched between the gate sidewalls to expose an upper surface of the gate electrode;
• and
• performing silicidation of the first and second impurity regions and the gate electrode.