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US 2006/0220123 A1Published application
Chip scale surface mounted device and process of manufacture
AssigneeInternational Rectifier Corporation
InventorsMartin Standing, Hazel Schofield
Life of this patent
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Abstract
A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
Claims20
A semiconductor device package comprising:
- a power semiconductor device, said power semiconductor device including a first power electrode on one major surface thereof, and a second power electrode on a second opposing major surface thereof;
- a passivation layer over said second power electrode of said power semiconductor device;
- at least one solderable body over said second power electrode of said power semiconductor device;
- and
- a conductive clip, said conductive clip having a web portion electrically and mechanically connected to said first power electrode of said power semiconductor device and at least one connection surface that faces a same direction as said at least one solderable body.
2 more elements
Dependencies are inferred from the claim text.