High voltage LDMOS device with counter doping
AssigneeImpinj, Inc.
InventorAndrew Horch
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Abstract
LDMOS structures and methods for fabricating them includes a counter dopant implant region in a drain well. According to another aspect, an LDMOS device includes a graded junction region in the LDMOS device's channel region. The counter dopant implant region may extend from the drain portion into the graded junction region. The counter dopant implant region can be formed using an implantation process that is already part of a standard MOS fabrication process. For example, in one embodiment, an implantation process that is used to adjust the threshold voltage (Vt) is used to form the counter doped region in the channel region of the LDMOS device.
Claims32
A n-channel field effect transistor, comprising:
- a p type substrate;
- a p− well disposed in said substrate;
- a first n+ doped region disposed in said p− well;
- a first terminal coupled to said first n+ doped region;
- an n− well disposed in said substrate;
- a second n+ doped region disposed in said n− well;
- a second terminal coupled to said second n+ doped region;
- a gate oxide layer disposed over at least a portion of:
- said p− well, and said n− well;
- a gate disposed over at least a portion of said gate oxide layer;
- and
- a counter dopant region with at least a portion disposed in said n− well between said second n+ doped region and said p= well.
A p-channel field effect transistor, comprising:
- a n type substrate;
- a n− well disposed in said substrate;
- a first p+ doped region disposed in said p− well;
- a first terminal coupled to said first p+ doped region;
- an p− well disposed in said substrate;
- an isolator disposed in said p− well;
- a counter dopant region with at least a portion disposed in said n− well between said first isolator and said n− well;
- a second p+ doped region disposed in said n− well;
- a second terminal coupled to said second p+ doped region;
- a gate oxide layer disposed over at least a portion of:
- said n− well, said p− well, and said isolator;
- and
- a gate disposed over at least a portion of said gate oxide layer.
A non-self aligned laterally diffused metal oxide semiconductor (LDMOS) device comprising a source, drain, gate, substrate and counter dopant region, wherein the drain includes a well implant region of opposite polarity to that of the substrate and a drain contact region disposed in the well implant region, the drain extending under the gate, and wherein the counter dopant region has at least a portion disposed in the Well implant region between the drain contact region and the source.
The non-self aligned LDMOS device of claim 19 further comprising an isolator disposed in the well implant region between the drain contact region and the counter dopant region.
A method of fabricating a field effect transistor, comprising:
- forming a p− well in a substrate;
- forming an n− well in said substrate;
- forming a gate oxide layer over at least a portion of:
- said p− well, said graded junction region, and said n− well;
- forming a gate disposed over at least a portion of said gate oxide layer;
- and
- forming a first n+ doped region in said p− well and a second n+ doped region in said n− well;
- and
- forming a counter dopant region with at least a portion disposed in said n− well between said second n+ doped region and said p− well;
Dependencies are inferred from the claim text.