P-channel MOS transistor, semiconductor integrated circuit device and fabrication process thereof

A semiconductor integrated circuit device comprising:

• a silicon substrate defined with a first device region including a first channel region and a second device region including a second channel region by a device isolation region;
• an n-channel MOS transistor formed on said first device region, comprising:
• a first gate electrode of n-type formed on said silicon substrate via a first gate insulation film in correspondence to a first channel region;
• a source extension region of n-type and a drain extension region of n-type formed in a part of said silicon substrate corresponding to said first device region at respective lateral sides of said first channel region;
• and a source region and a drain region of n-type formed in a part of said silicon substrate corresponding to said first device region at respective lateral sides of said first gate electrode at outer sides of sidewall insulation films formed on respective sidewall surfaces of said first gate electrode so as to overlap partially with said source extension region of n-type and said drain extension region of n-type respectively;
• a p-channel MOS transistor formed on said second device region, comprising:
• a second gate electrode of p-type formed on said silicon substrate via a second gate insulation film in correspondence to a second channel region;
• a source extension region of p-type and a drain extension region of p-type formed in a part of said silicon substrate corresponding to said second device region at respective lateral sides of said second channel region;
• and a source region and a drain region of p-type formed in a part of said silicon substrate corresponding to said second device region at respective lateral sides of said second gate electrode at outer sides of sidewall insulation films formed on respective sidewall surfaces of said second gate electrode so as to overlap partially with said source extension region of p-type and said drain extension region of p-type respectively;
• an interlayer insulation film extending over said first and second device regions on said silicon substrate so as to cover said n-channel MOS transistor and said p-channel MOS transistor;
• first and second contact plugs formed in said interlayer insulation film in correspondence to said source region and drain region of n-type;
• third and fourth contact plugs formed in said interlayer insulation film in correspondence to said source region and drain region of p-type, said first and second contact plugs carrying first and second tensile stress source of any of a metal and a metal compound on respective tip end parts thereof in contact with said source region of n-type and said drain region of n-type,
• said third and fourth contact plugs carrying third and fourth compressive stress source of any of a metal and a metal compound on respective tip end parts thereof in contact with said source region of p-type and said drain region of p-type.

A method of fabricating a p-channel MOS transistor, comprising the steps of:

• forming a gate electrode on a silicon substrate in correspondence to a channel region;
• forming a source region of p-type and a drain region of p-type in said silicon substrate at respective lateral sides of said gate electrode;
• forming recess regions in each of said source region and drain region of p-type;
• covering a surface said recess regions with a refractory metal silicide film along the shape of said recess regions;
• and
• depositing a metal or metal compound film on said refractory metal silicide film so as to fill said recess regions under a condition such that said metal or metal compound film accumulates therein a compressive stress.

A method of fabricating a semiconductor integrated circuit device including therein a p-channel MOS transistor and an n-channel MOS transistor on a silicon substrate defined with first and second device regions by a device isolation region, comprising the steps of:

• forming an n-channel MOS transistor having an n-type source region and an n-type drain region on said device region and forming a p-channel MOS transistor having a p-type source region and a p-type drain region on said second device region;
• forming an interlayer insulation film on said silicon substrate over said first and second device regions so as to cover said n-channel MOS transistor and said p-channel MOS transistor;
• forming first and second conductive plugs in said interlayer insulation film in contact respectively with said source region of n-type and said drain region of n-type, such that said first and second conductive plugs filling first and second contact holes formed in said interlayer insulation film respectively in correspondence said source region of n-type and said drain region of n-type;
• crystallizing said first and second conductive plugs by a thermal annealing process;
• forming, after said step of crystallization, third and fourth contact holes in said interlayer insulation film so as to expose said p-type source region and said p-type drain region respectively;
• and
• filling at least a bottom part of said third and fourth contact holes with a metal or a metal compound,
• said metal or metal compound being deposited under a condition that a compressive stress is accumulated therein.