Tunneling-enhanced floating gate semiconductor device
AssigneeImpinj, Inc.
InventorsBin Wang, Yanjun Ma
Life of this patent
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Abstract
Tunneling-enhanced, floating gate semiconductor devices and methods for forming such devices are described. In one embodiment, a p-n junction device is formed with a floating gate that is partially doped with n- and p-type impurities. Two regions on either side of an n+ doped region in the floating gate and a surface region on a substrate are implanted with the impurities based on a number of predetermined configurations. In another embodiment, a transistor type semiconductor device is configured with implanted impurities in two regions of its floating gate as well as two surface regions in its substrate. Enhanced tunneling junction enables use of lower tunneling voltages in applications such as programming NVM cells.
Claims43
A tunneling-enhanced floating gate device, comprising:
- a substrate that includes impurities of p-type;
- an n-well within the substrate that includes impurities of n-type;
- a floating gate structure disposed over the n-well, wherein the floating gate structure includes a first region, a centrally located second region that is doped with implants of n-type impurities, and a third region;
- and
- a first surface region in the n-well, wherein the first surface region is located about the third region of the floating gate structure.
A method for creating a tunneling-enhanced floating gate device, comprising:
- forming a substrate that includes impurities of p-type;
- forming an n-well within the substrate that includes impurities of n-type;
- forming a floating gate structure disposed over the n-well, wherein the floating gate structure includes a first region, a centrally located second region that is doped with implants of n-type impurities, and a third region;
- forming a first surface region in the n-well, wherein the first surface region is located about the third region of the floating gate structure;
- and
- forming a second surface region that is located about the first surface region away from the floating gate structure, wherein the second surface region is doped with implants of n-type impurities.
A tunneling-enhanced floating gate device, comprising:
- a substrate that includes impurities of p-type;
- an n-well within the substrate that includes impurities of n-type;
- a first surface region in the n-well;
- a second surface region in the n-well;
- a floating gate structure disposed over a region in the n-well defined by the first surface region and the second surface region, wherein the floating gate structure includes a first region, a centrally located second region that is doped with implants of n-type impurities, and a third region;
- and
- a third surface region that is located about the second surface region away from the floating gate structure, wherein the third surface region is doped with implants of n-type impurities.
A method for creating a tunneling-enhanced floating gate device, comprising:
- forming a substrate that includes impurities of p-type;
- forming an n-well within the substrate that includes impurities of n-type;
- forming a first surface region in the n-well;
- forming a second surface region in the n-well;
- forming a floating gate structure disposed over a region in the n-well defined by the first surface region and the second surface region, wherein the floating gate structure includes a first region, a centrally located second region that is doped with implants of n-type impurities, and a third region;
- and
- forming a third surface region that is located about the second surface region away from the floating gate structure, wherein the third surface region is doped with implants of n-type impurities.
Dependencies are inferred from the claim text.