Single transistor floating body DRAM cell having recess channel transistor structure and method of fabricating the same

A single transistor floating body dynamic random access memory (DRAM) cell, comprising:

• an integrated circuit substrate;
• a barrier layer on the substrate;
• and
• a recess channel transistor on the barrier layer, the recess channel transistor comprising:
• an N-type source region;
• an N-type drain region spaced apart from the source region;
• a P-type floating body between the barrier layer and the source region and the drain region, the floating body including a recess region extending across the floating body between the source region and the drain region;
• and
• a gate electrode in the recess region.

A method of fabricating a single transistor floating body dynamic random access memory (DRAM) cell, comprising:

• forming a barrier layer on a semiconductor substrate;
• forming a body layer on the barrier layer;
• forming an isolation layer defining a floating body region within the body layer;
• forming a recess region in the floating body region;
• forming a gate electrode in the recess region;
• and
• implanting impurity ions of a first conductivity type into a portion of the floating body region on a first side of the recess region to define a source region and into a portion of the floating body on an opposite side of the recess region to define a drain region to provide a floating body.