Phase-change semiconductor memory device and method of programming the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSang-beom Kang, Du-eung Kim, Hyung-rok Oh
Life of this patent
Estimating the term…
Abstract
In one aspect, a semiconductor memory device includes a plurality of phase-change memory cells which are programmed according to a write current applied to the phase-change memory cells, a voltage boosting circuit which receives a first voltage and outputs a boosted voltage which is greater than the first voltage, and a write driver which receives the boosted voltage and which generates the write current from the boosted voltage. In another aspect, the write driver generates the write current corresponding to one of a set current pulse and a reset current pulse, and at least one of the set current pulse and the reset current pulse is gradually increased.
Claims19
A semiconductor memory device, comprising:
- a plurality of phase-change memory cells which are programmed according to a write current applied to the phase-change memory cells;
- a voltage boosting circuit which receives a first voltage and outputs a boosted voltage which is greater than the first voltage;
- and
- a write driver which receives the boosted voltage and which generates the write current from the boosted voltage.
A method of programming memory cells, the memory cells each including a phase-change material which is responsive to a write current to be selectively programmed into one of at least two states, said method comprising:
- selectively generating one of a set current pulse and a reset current pulse, wherein a magnitude of at least one of the set current pulse and the reset current pulse is gradually increased;
- and
- generating the write current corresponding to the set current pulse to program the phase-change material into a first state, and generating the write current corresponding to the reset current pulse to program the phase-change material into a second state.
A semiconductor memory device, comprising:
- a memory cell array including memory cells which store data in response to a write current;
- and
- a write driver which generates the write current from a boosted voltage and applies the write current to the memory cells in response to a set current pulse or reset current pulse.
Dependencies are inferred from the claim text.