Method and system for variable thread allocation and switching in a multithreaded processor

A system for processing instructions on a multithreaded processor, the multithreaded processor for processing a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor, the system comprising:

• control circuitry for determining the operating frequency, F, at which said multithreaded processor operates;
• issue logic for determining a variable thread switch timeout state for triggering the switching of the processing among said plurality of active threads, said variable thread switch timeout state being variable such that each of said plurality of active threads operates at a frequency of an allocated portion of said frequency, F, said allocated portion determined at least in part for optimizing operation of said multithreaded processor;
• and
• said issue logic further for switching said processing from a first one of said active threads to a next one of said active threads upon the occurrence of said variable thread switch timeout state.

A digital signal processor for processing instructions on a multithreaded processor, the multithreaded processor for processing a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor, the digital signal processor comprising:

• means for determining the operating frequency, F, at which said multithreaded processor operates;
• means for determining a variable thread switch timeout state for triggering the switching of the processing among said plurality of active threads, said variable thread switch timeout state being variable such that each of said plurality of active threads operates at a frequency of an allocated portion of said frequency, F, said allocated portion determined at least in part for optimizing operation of said multithreaded processor;
• and
• means for switching said processing from a first one of said active threads to a next one of said active threads upon the occurrence of said variable thread switch timeout state.

An article of manufacture having computer readable program code means embodied therein for processing instructions on a multithreaded processor, the multithreaded processor for processing a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor, the computer readable program means in said article of manufactured comprising the steps of:

• computer readable program means for determining the operating frequency, F, at which said multithreaded processor operates;
• computer readable program means for determining a variable thread switch timeout state for triggering the switching of the processing among said plurality of active threads, said variable thread switch timeout state being variable such that each of said plurality of active threads operates at a frequency of an allocated portion of said frequency, F, said allocated portion determined at least in part for optimizing operation of said multithreaded processor;
• and
• computer readable program means for switching said processing from a first one of said active threads to a next one of said active threads upon the occurrence of said variable thread switch timeout state.