Memory having a portion that can be switched between use as data and use as error correction code (ECC)

A memory comprising:

• a memory array, the memory array including a first plurality of memory cells located in a first set of columns and a second plurality of memory cells located in a second set of columns, wherein the memory array includes a plurality of word lines with memory cells of the first plurality of memory cells and memory cells of the second plurality of memory cells coupled to each word line of the plurality of word lines;
• and
• means for, in a first mode providing data stored in memory cells of the second plurality of memory cells to a data bus, and in a second mode providing data stored in memory cells of the first plurality of memory cells coupled to a word line and error correction code information stored in memory cells of the second plurality coupled to the word line to an error correction code circuit.