Integrated circuit margin stress test system
AssigneeSilicon Design Solution, Inc.
InventorsKevin LeClair, Thomas Wik, Chuong Le, Hieu Nguyen, Duytan Tran, Kevin Bligh
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Abstract
Systems and methods are disclosed for testing a synchronous memory system by electrically stressing one or more electrical conditions of the component circuits; providing a Built-In Self-Test (BIST) controller to control the electrical stress during device testing; and providing a test stimuli during testing. In another aspect, the memory system testing includes setting a self-timed control input of the memory system to a predetermined self timed period value; and testing the memory based on the predetermined self timed period value.
Claims31
A system for testing an integrated circuit device having component circuits therein, comprising:
- a stress circuit to vary one or more electrical conditions of the component circuits;
- an on-chip test controller coupled to the stress circuit to control an electrical stress during device testing;
- and
- an external tester coupled to the on-chip test controller to provide the electrical stress and to provide test stimuli during testing, the external tester leaving the integrated circuit device in an unstressed mode during field operation.
A memory system, comprising:
- a synchronous memory array having self-timed period (STP) control input;
- and
- a test controller coupled to the self-timed control input of the synchronous memory array to vary the memory's self-time period during testing.
A method for testing a synchronous memory system having a self-timed control input, comprising:
- a. setting the self-timed control input to a predetermined self timed period value;
- and
- b. testing the synchronous memory based on the predetermined self timed period value.
A method for testing embedded synchronous memory in an integrated circuit, the method comprising:
- generating an expected data value;
- setting a self timed period value for the synchronous memory;
- delivering test data, separate from control data and address data, to the memory;
- reading an actual data value from the memory corresponding to the delivered test data;
- and
- comparing the actual data value to the expected data value.
A method for testing an integrated circuit device having component circuits therein, comprising:
- electrically stressing one or more electrical conditions of the component circuits;
- providing a Built-In Self-Test (BIST) controller to control the electrical stress during device testing;
- and
- providing a test stimuli during testing.
Dependencies are inferred from the claim text.