Circuit automatic generation apparatus and method

A circuit automatic generation apparatus of a semiconductor integrated circuit for connecting signals of a plurality of function circuits to generate a high-layer circuit, the circuit automatic generation apparatus comprising:

• means for retaining input/output information of each of the function circuits and circuit information to which each of the function circuits is connected and input/output information of the high-layer circuit and circuit information to which the high-layer circuit is connected;
• means for collating the signal connection relationship of the function circuit and determining the presence or absence of a connection defect;
• and
• means for generating the high-layer circuit from the input/output information of the function circuit and circuit information to which the function circuit is connected and the input/output information of the high-layer circuit and circuit information to which the high-layer circuit is connected.

A circuit automatic generation method of a semiconductor integrated circuit for connecting signals of a plurality of function circuits to generate a top-layer circuit, the circuit automatic generation method comprising the steps of:

• collating the signal connection relationship of the function circuit and determining the presence or absence of a connection defect;
• generating a test mode generation circuit in response to test mode generation specifications for generating a test mode signal to identify a plurality of operation modes containing the usual operation time and the test operation time;
• generating a function circuit to which test specifications are added in response to the test specifications added to the function circuit;
• generating a terminal test circuit in response to terminal test specifications for specifying input/output directions of terminals and circuit terminal information to which the terminals are connected in response to the test mode signal;
• and
• generating the top-layer circuit from the test mode generation specifications, the terminal test specifications, the input/output information of the function circuit and circuit information to which the function circuit is connected, the test specifications added to the function circuit, and the input/output information of the top-layer circuit and circuit information to which the top-layer circuit is connected.