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US 2006/0218452 A1Published application
Area efficient BIST system for memories
AssigneeCisco Technology, Inc.
InventorsCharles Njinda, Shalesh Thusoo, Hao Wang
Life of this patent
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AssigneeCisco Technology, Inc.
InventorsCharles Njinda, Shalesh Thusoo, Hao Wang
Estimating the term…
A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design for Test Assist Logic (DAL) block. The DAL associated with any particular memory array recognizes commands from the BIST that are for the associated memory array, controls the execution of write/read commands for the associated array and sends data read from the memory array along with appropriate commands to the comparator after a latency that is appropriate for the associated array Thus, there are standardized commands from the BIST, but each DAL executes these commands in a manner appropriate for the memory array (or arrays) associated with he particular DAL.
1) A system for testing memory arrays in circuit blocks on an integrated circuit, each of said memory arrays having an array address, said system including:
11) A method of testing memory arrays in circuit blocks on an integrated circuit, each of said memory arrays having an array address, said circuit blocks being connected by a serial bus, said integrated circuit including a BIST controller connected to a beginning stage of said serial bus and a comparator connected to an end stage of said serial bus, said method including the steps of:
21) A system for testing memory arrays in circuit blocks on an integrated circuit, each of said memory arrays having an array address, said system including:
Dependencies are inferred from the claim text.