Semiconductor integrated circuit device, debug system, microcomputer, and electronic apparatus
AssigneeSeiko Epson Corporation
InventorMakoto Kudo
Life of this patent
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Abstract
An integrated circuit device including an internal debug module for on-chip debugging while communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprises; a first debug terminal coupled to a first communication line; a first common control unit that controls using the first communication line for both transmission of a serial data signal corresponding debug data for sending, which is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging and transmission of a run/break state signal, which shows a run state or a break state of the CPU.
Claims20
An integrated circuit device including an internal debug module for on-chip debugging while communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprises;
- a first debug terminal coupled to a first communication line;
- a first common control unit that controls using the first communication line for both transmission of a serial data signal corresponding debug data for sending, which is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging and transmission of a run/break state signal, which shows a run state or a break state of the CPU.
An integrated circuit device including an internal debug module for on-chip debugging while synchronously communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprises;
- a second debug terminal coupled to a second communication line;
- a second common control unit that controls using the second transmission line for both transmission of a clock signal for synchronization, which is necessary for on-chip debugging with the pin-saving debug tool, and transmission of a run/break state signal, which shows a run state or a break state of the CPU.
A debug system comprising a pin-saving debug tool and a target system, which is an object to be debugged by the debug tool, wherein the target system includes an integrated circuit device including an internal debugging module for on-chip debugging while communicating with the pin-saving debug tool, and a CPU, wherein the integrated circuit device includes:
- a first main debug terminal coupled to a first communication line;
- a first main common control unit that controls using the first main communication line for both transmission of serial data signal corresponding debug data for transmission, which is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging, and transmission of a run/break state signal, which shows a run state or a break state of the CPU,
- and wherein the debug tool includes:
- a first sub debug terminal coupled to the first communication line;
- and
- a first sub common control unit that controls using the first communication line for both transmission of a serial data signal corresponding debug data for transmission, which is sent and/or received to and/or from the integrated circuit during on-chip debugging, and receipt of a run/break state signal, which shows a run state or a break state of the CPU.
A debug system comprising a pin-saving debug tool and a target system, which is an object to be debugged by the debug tool, wherein the target system comprises an integrated circuit device including an internal debugging module for on-chip debugging while communicating with the pin-saving debug tool, and a CPU wherein the integrated circuit device includes:
- a second debug terminal coupled to a second communication line;
- a second main common control unit that controls using the second transmission line for both transmission of a clock signal for synchronization, which is necessary for on-chip debugging with the pin-saving debug tool, and transmission of a run/break state signal, which shows a run state or a break state of the CPU and wherein the debug tool includes a second sub common control unit that controls using the second transmission line for both transmission of a clock signal for synchronization, which is necessary for on-chip debugging with the pin-saving debug tool, and receipt of a run/break state signal, which shows a run state or a break state of the CPU.
Dependencies are inferred from the claim text.