US 2006/0218381 A1 · Rounding correction for add-shift-round instruction with dual-use source operand for DSP

Abstract

A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified. An ADDSRN instruction which performs addition and right shifting and rounding, in which one of the source operands is an encoded immediate which specifies the shift count N. The processor corrects after the addition and shifting for an absent rounding bias added 2N-1. The ADDSRN instruction is used in accelerating digital signal processing code sequences of the form dest:=(A+B+C+D . . . +M+2) >>N

Claims12

Dependent claims

A processor for executing an arithmetic shift instruction which specifies a plurality of source operands and a shift count, the processor comprising:

an adder coupled to receive the plurality of source operands, for producing a result;
a shifter coupled to receive the shift count and the result, for shifting the result by the shift count to generate a shifted result;
logic coupled to receive the result and the shift count, for generating a control signal;
and
an incrementer coupled to receive the shifted result, for selectably incrementing the shifted result in response to the control signal.

2 more elements

Dependencies are inferred from the claim text.

Rounding correction for add-shift-round instruction with dual-use source operand for DSP

Life of this patent

Rounding correction for add-shift-round instruction with dual-use source operand for DSP

Life of this patent

Abstract

Claims12