Method and system for encoding variable length packets with variable instruction sizes

A system for operation in association with a digital signal processor for encoding and processing instructions of mixed lengths, the system comprising:

• a memory for encoding a plurality of instructions of a first length;
• said memory circuitry further for encoding a plurality of instructions of a second length;
• encoding circuitry and instructions associated with said memory for encoding a header comprising at least one instruction length bit, said at least one instruction bit for distinguishing between said plurality of instructions of a first length and said plurality of instructions of a second length;
• said encoding circuitry and instructions further for associating at least one said header with each instruction of said plurality of instructions of a first length and at least one said header with each instruction of said plurality of instructions of a second length to form a second encoded instruction;
• register circuitry and instructions for processing in a mixed stream said plurality of instructions of a first length and said plurality of instructions of a second length;
• and
• said register circuitry and instructions further for distinguishing between each of said plurality of instructions of a first length and said plurality of instructions of a second length according to said at least one instruction length bit of said correspondingly associated header.

A digital signal processor for operation in association with an personal electronics device for encoding and processing instructions of mixed lengths, the digital signal processor comprising:

• means for encoding a plurality of instructions of a first length;
• means for encoding a plurality of instructions of a second length;
• means for encoding a header comprising at least one instruction length bit, said at least one instruction bit for distinguishing between said plurality of instructions of a first length and said plurality of instructions of a second length;
• means for associating at least one said header with each instruction of said plurality of instructions of a first length and at least one said header with each instruction of said plurality of instructions of a second length to form a second encoded instruction;
• means for processing in a mixed stream said plurality of instructions of a first length and said plurality of instructions of a second length;
• and
• means for distinguishing between each of said plurality of instructions of a first length and said plurality of instructions of a second length according to said at least one instruction length bit of said correspondingly associated header.

A computer usable medium having computer readable program code means embodied therein for processing instructions on digital signal processor operating in association with a wireless handset, the computer usable medium comprising:

• computer readable program code means for encoding a plurality of instructions of a first length;
• computer readable program code means for encoding a plurality of instructions of a second length;
• computer readable program code means for encoding a header comprising at least one instruction length bit, said at least one instruction bit for distinguishing between said plurality of instructions of a first length and said plurality of instructions of a second length;
• computer readable program code means for associating at least one said header with each instruction of said plurality of instructions of a first length and at least one said header with each instruction of said plurality of instructions of a second length to form a second encoded instruction;
• computer readable program code means for processing in a mixed stream said plurality of instructions of a first length and said plurality of instructions of a second length;
• and
• computer readable program code means for distinguishing between each of said plurality of instructions of a first length and said plurality of instructions of a second length according to said at least one instruction length bit of said correspondingly associated header.