Integrated circuit device

An integrated circuit device having a CPU which executes given processing based on an instruction code, the integrated circuit device comprising:

• an instruction address bus used to supply an instruction address to a memory;
• and
• an instruction address supply line used to supply an instruction address output from a coprocessor to the CPU,
• the CPU including:
• a fetch section which fetches an instruction code;
• and
• an instruction address select circuit which receives an instruction address supplied through the instruction address supply line and an instruction address supplied from the fetch section, and supplies one of the instruction addresses to the instruction address bus.

An integrated circuit device having a CPU which executes given processing based on an instruction code, the integrated circuit device comprising:

• first and second register data supply lines used to respectively supply first and second register data output from a coprocessor to the CPU,
• the CPU including:
• a register file including a plurality of registers;
• and
• a first register data select circuit which receives the first register data supplied through the first register data supply line and CPU internal data, and supplies one of the first register data and the CPU internal data to the register file, and
• the second register data output from the coprocessor being supplied to the register file through the second register data supply line.

An integrated circuit device having a CPU which executes given processing based on an instruction code, the integrated circuit device comprising:

• a data address supply line used to supply a data address output from a coprocessor to the CPU,
• the CPU including:
• a load/store section which writes data into a memory by supplying a data address to the memory through a data address bus and supplying write data through a write data bus;
• and
• a data address select circuit which receives a data address supplied through the data address supply line and a data address output from the load/store section, and supplies one of the data addresses to the data address bus.

An integrated circuit device having a CPU which executes given processing based on an instruction code, the integrated circuit device comprising:

• a write data supply line used to supply write data output from a coprocessor to the CPU,
• the CPU including:
• a load/store section which writes data into a memory by supplying a data address to the memory through a data address bus and supplying write data through a write data bus;
• and
• a write data select circuit which receives write data supplied through the write data supply line and write data output from the load/store section, and supplies one of the write data to the write data bus.

An integrated circuit device having a CPU which executes given processing based on an instruction code, the integrated circuit device comprising:

• a read data supply line used to supply read data output from a coprocessor to the CPU,
• the CPU including:
• a load/store section which reads data from a memory by supplying a data address to the memory through a data address bus and receiving read data through a read data bus;
• and
• a read data select circuit which receives read data supplied through the read data supply line and read data supplied from the read data bus, and supplies one of the read data to the load/store section.