Methods and apparatus for efficiently sharing memory and processing in a multi-processor
OwnerGerald Pechanekinventor
Life of this patent
Estimating the term…
Abstract
A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify any source operand addresses or target operand addresses. The source operands and target operands for arithmetic/logic execution units are provided by independent load instruction operations and independent store instruction operations.
Claims20
A network of nodes identified according to a G×H matrix with gε{0,1, . . . ,G−1} and hε{0,1, . . . ,H−1}, the network comprising:
- a first set of nodes {A0,0, A0,1, . . . , A0,H−1, A1,0, A1,1, . . . , A1,H−1, . . . , AG−1,H−1}, each node Ag,h having an output;
- a second set of nodes {R0,0, R0,1, . . . , R0,H−1, R1,0, R1,1, . . . , R1,H−1, . . . , RG−1,H−1}, each node Rg,h having an output and each node Rg,h having a first input connected to the output of node Ag,h, a second input connected to the output of node Ag,h+1, and a third input connected to the output of node Ag,h−1, where h+1 wraps to 0 when h+1═H and h−1 wraps to H−1 when h−1=−1;
- and
- a third set of nodes {S0,0, S0,1, . . . , S0,H−1, S1,0, S1,1, . . . , S1,H−1, . . . , SG−1,H−1}, each node Sg,h having an output and each node Sg,h having a first input connected to the output of node Rg,h, a second input connected to the output of node Rg+1,h, and a third input connected to the output of node Rg−1,h, where g+1 wraps to 0 when g+1=G and g−1 wraps to G−1 when g−1=−1.
A method of constructing a network of nodes N(i)g,h identified by gε{0,1, . . . ,G−1}, hε{0,1, . . . ,H−1}, N(0) identifies nodes in a first set of nodes, N(1) identifies nodes in a second set of nodes, and N(2) identifies nodes in a third set of nodes, the method comprising:
- connecting for i=0 an output of each node N(i)g,h to an input of node N(i+1)g,h and to an input of node N(i+1)g,h+1 and to an input of node N(i+1)g,h−1 where h+1 wraps to 0 when h+1=H and h−1 wraps to H−1 when h−1=−1;
- and
- connecting for i=1 an output of each node N(i)g,h to an input of node N(i+1)g,h and to an input of node N(i+1)g+1,h and to an input of node N(i+1)g−1,h where g+1 wraps to 0 when g+1=G and g−1 wraps to G−1 when g−1=−1.
A processor node operative to execute arithmetic instructions comprising:
- an arithmetic instruction decoder that decodes arithmetic instructions responsive to arithmetic instructions having a format containing only execution unit operation information without use of source operand or target operand fields;
- and
- an execute unit that executes the decoded arithmetic instruction with source operands provided as an input to the arithmetic execution unit, the source operands specified by a load instruction independent of the arithmetic instruction and the execution unit generates results of the arithmetic execution that are provided as an output of the arithmetic execution unit, the storage of the results specified by a store instruction independent of the arithmetic instruction.
Dependencies are inferred from the claim text.