Enforcing strongly-ordered requests in a weakly-ordered processing system

A bus interconnect, comprising:

• a bus switch configured to interface a plurality of processors to a plurality of memory devices in a weakly-ordered processing system, each of the processors being configured to generate memory access requests to one or more of the memory devices, and each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request;
• and
• a controller configured to enforce ordering constraints on the memory access requests based on the attributes.

A method of enforcing strongly-ordered memory access requests in a weakly-ordered processing system, comprising:

• receiving, from a plurality of processors, memory access requests for a plurality of memory devices, one of the memory access requests having a memory attribute indicating a strongly-ordered memory access request;
• and
• enforcing an ordering constraint on the strongly-ordered memory access request in relation to the other memory access requests in response to the attribute.