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AssigneeQUALCOMM Incorporated
InventorsThomas Sartorius, Victor Augsburg, James Dieffenderfer
Estimating the term…
A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.
A method of managing a cache including at least one entry managed according to a copy-back algorithm, comprising:
A processor, comprising:
The method of claim 7 wherein the cache is divided into two or more banks, and further comprising two or more bank-global modified indicators, each indicating whether any copy-back entry in an associated bank contains modified data, and wherein the controller is operative to replace a cache entry in a bank without first reading the entry, if the associated bank-global modified indicator indicates that no copy-back cache entry in the bank contains modified data.
A method of processing a cache miss in a cache including at least one entry managed according to a copy-back replacement algorithm, comprising:
Dependencies are inferred from the claim text.