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US 2006/0218352 A1Published application
Cache eviction technique for reducing cache eviction traffic
AssigneeIntel Corporation
InventorsChristopher Shannon, Mark Rowland, Ganapati Srinivasa
Life of this patent
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Abstract
A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.
Claims30
An apparatus comprising:
- an upper level cache having an upper level cache line;
- at least two lower level caches each having a lower level cache line;
- an eviction unit to evict the upper level cache line depending only on a number of cache line evictions within the lower level caches that could possibly result from evicting the upper level cache line.
A system comprising:
- a plurality of bus agents, at least one of the plurality of bus agents comprising an inclusive cache hierarchy including an upper level cache and a plurality of lower level caches, cache line evictions from the upper level cache are to be based only on the number of resulting lower level cache evictions could possibly result from the upper level cache line evictions.
A method comprising:
- determining whether to evict an upper level cache line within an inclusive cache memory hierarchy based solely on the amount of resultant cache coherency traffic between the upper level cache and lower level caches;
- evicting the upper level cache line.
An apparatus comprising:
- an upper level cache having an upper level cache line;
- a plurality of lower level caches having a plurality of lower level cache line;
- an eviction means for evicting the upper level cache way depending on a number of lower level caches affected by the eviction of the upper level cache way.
Dependencies are inferred from the claim text.