Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system

A bus interconnect, comprising:

• a bus switch configured to interface a plurality of processors to a plurality of memory devices in a weakly-ordered processing system, each of the processors configured to generate memory access requests to one or more of the memory devices;
• and
• a controller configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the controller can confirm have no unexecuted memory access requests from the originating processor.

A method of enforcing strongly-ordered memory access requests in a weakly-ordered processing system, comprising:

• receiving, from a plurality of processors, memory access requests for a plurality of memory devices, one of the memory access requests from an originating processor to a target memory device being a strongly-ordered request;
• and
• enforce an ordering constraint for the strongly-ordered memory access request by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices in which it can be confirmed that there are no unexecuted memory access requests from the originating processor.