Semiconductor integrated circuit
AssigneeFujitsu Limited
InventorSatoshi Matsui
Life of this patent
Estimating the term…
Abstract
When needing to make write accesses to both upper and lower sides of a counter in a timer, a CPU accesses the lower side last, and accesses the lower side first when needing to make read accesses thereto. The timer stores data of the data bus in the write buffer at the write access to the upper side, and writes the data of the data bus to the lower side and writes the data of the write buffer to the upper side at the write access to the lower side. At the read access to the lower side of the counter, the timer reads the data of the lower side for output to the data bus and reads the data of the upper side for storage in the read buffer. At the read access to the upper side, it outputs data of the read buffer to the data bus.
Claims10
A semiconductor integrated circuit comprising:
- a data bus;
- a bus master which performs an access operation in a data width same as that of said data bus;
- and
- a macro block which has a data width larger than said data bus and includes a register whose lower side is connected to said data bus, a write buffer storing therein write data to an upper side of said register, and a read buffer storing therein read data from the upper side of said register, wherein:
- said bus master accesses a lower side of said register last when needing to make write accesses to both of the upper and lower sides of said register, and said bus master accesses the lower side of said register first when needing to make read accesses to both of the upper and lower sides of said register;
- said macro block stores data of said data bus in said write buffer in response to a write access of said bus master to the upper side of said register, and writes the data of said data bus to the lower side of said register and writes the data of said write buffer to the upper side of said register in response to a write access of said bus master to the lower side of said register;
- and
- said macro block reads and outputs the data of the lower side of said register to said data bus and reads and stores the data of the upper side of said register in said read buffer in response to a read access of said bus master to the lower side of said register, and outputs the data of said read buffer to said data bus in response to a read access of said bus master to the upper side of said register.
Dependencies are inferred from the claim text.