Interface circuit, system, and method for interfacing between buses of different widths
AssigneeVIA Technologies, Inc.
InventorDavid Boudreau
Life of this patent
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Abstract
Interface circuits and methods for transferring data between buses of different widths are disclosed herein. The interface circuits comprise first control logic configured to provide a selection signal to a plurality of first distribution devices. Each of the first distribution devices controls communication between a respective byte register and a respective byte location on a first bus. The interface circuit further comprises second control logic configured to provide a selection signal to a second distribution device. The second distribution device controls communication between the plurality of byte registers and a second bus, where the second bus has a width of fewer bytes than the first bus.
Claims44
An interface circuit for transferring data between buses of different widths, the interface circuit comprising:
- a plurality of byte registers;
- first control logic configured to provide a first selection signal to a plurality of first distribution devices, each of the first distribution devices controlling communication between one of the byte registers and one of a plurality of byte locations on a first bus;
- and
- second control logic configured to provide a second selection signal to a second distribution device, the second distribution device controlling communication between one of the plurality of byte registers and a second bus, the second bus having a width of a fewer number of bytes than the width of the first bus.
A system for interfacing a first bus with a second bus, the system comprising:
- a plurality of temporary storage components;
- first means for transferring data between a first bus and at least one of the temporary storage components in a single clock cycle;
- second means for transferring data between a second bus and the at least one of the temporary storage components in a number of clock cycles.
A method for interfacing a first bus with a second bus, the method comprising:
- transferring a plurality of bytes of data between a first bus and a corresponding number of registers in one clock cycle;
- and
- transferring the plurality of bytes of data between a second bus and the registers one byte per clock cycle;
- wherein the first bus has a greater width than the second bus.
Dependencies are inferred from the claim text.