System and method for communicating the synchronization status of memory modules during initialization of the memory modules

A method of initializing a memory system having a controller coupled to a plurality of memory hubs each of which includes a respective receiver, each receiver operable to utilize a respective receive clock signal, the method comprising:

• receiving predetermined test data at each of the memory hubs;
• capturing the predetermined test data at the receiver of each of the memory hubs, and wherein the act of capturing the predetermined test data in a first memory hub of the plurality of memory hubs comprises adjusting a phase of the respective receive clock signal utilized by the receiver in the first memory hub;
• transmitting an initialization complete signal from each of the memory hubs responsive to the capture of the predetermined test data in the respective memory hub;
• and
• receiving the initialization complete signal at the controller after each of the memory hubs has transmitted the initialization complete signal.

A memory module, comprising:

• a plurality of memory devices;
• and
• a memory hub coupled to the plurality of memory devices, the memory hub comprising:
• a receiver operable to receive predetermined test data, the receiver further operable to utilize an internal receive clock signal, the receiver comprising phase adjustment logic operable to adjust a phase of the receive clock signal to capture the predetermined test data;
• and
• a transmitter operable to transmit an initialization complete signal responsive to the capture of the predetermined test data.

A memory system, comprising:

• a memory hub controller operable to transmit predetermined test data and receive an initialization complete signal, the memory hub controller further operable to transition the memory system to normal operation responsive to the initialization complete signal;
• and
• a memory module coupled to the memory hub controller, the memory module comprising:
• a plurality of memory devices;
• and
• a memory hub coupled to the plurality of memory devices, the memory hub comprising:
• a receiver operable to receive the predetermined test data, the receiver further operable to utilize an internal receive clock signal, the receiver comprising phase adjustment logic operable to adjust a phase of the receive clock signal to capture the predetermined test data;
• and
• a transmitter operable to transmit the initialization complete signal responsive to the capture of the predetermined test data.