Memory access control circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsKazunori Okajima, Yasuyuki Tomida, Kunihiro Kaida
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Abstract
A data transfer request of a data processing device with respect to a synchronous memory is divided by a burst transfer length unit request dividing section into a plurality of data transfer requests in which a data transfer amount is an amount of data to be burst-transferred at a time and the data to be burst-transferred at a time is within a single memory bank. An assembling section assembles the divided data transfer requests into a plurality of new data transfer requests obtained by combining the divided data transfer requests, one for each memory bank.
Claims10
A memory access control circuit of controlling access of a data processing device to a memory, wherein the memory is a synchronous memory having a plurality of memory banks capable of being operated independently, and data can be burst-transferred in accordance with a clock signal, the memory access control circuit comprising:
- a burst transfer length unit transfer request dividing section of receiving a data transfer request with respect to the memory from the data processing device, and dividing the received data transfer request into a plurality of data transfer requests in which a data transfer amount is an amount of data to be burst-transferred at a time, and the data to be burst-transferred at a time is within a single memory bank;
- a transfer request assembling section of assembling the plurality of data transfer requests divided by the burst transfer length unit transfer request dividing section into a plurality of new data transfer requests obtained by combining the divided data transfer requests, one for each memory bank;
- a data transfer control section of controlling data transfer between the memory and the data processing device based on the new data transfer request.
Dependencies are inferred from the claim text.