High performance register accesses

A data register comprising:

• a data input;
• a data output;
• a Write_Select input;
• a Write_Valid input;
• a Read_Select input;
• a Read_Valid input;
• wherein said Write_Select input is a first control input effective for selectively placing said data register in a write mode of operation in response to a first logic signal if said Write_Valid input is actuated, and said data register disregards said Write_Select input if said Write_Valid input is not actuated;
• and
• wherein said Read_Select input is a second control input effective for placing said data register in a read mode of operation in response to a second logic signal if said Read_Valid input is actuated, and said data register disregards said Read_Select input if said Read_Valid input is not actuated.

A register access system, comprising:

• A) a data processing unit having:
• i) data output nodes;
• ii) address output nodes;
• iii) a Write_Select output for initiating a write operation;
• iv) a Read_Select output for initiating a read operation;
• B) a data bus coupled to said data output node;
• C) an address bus coupled to said address output nodes;
• E) at least one data register module coupled to said data bus, address bus, Write_Select output and Read_Select output, each data register module including:
• 1) at least one register_latch bank;
• 2) an operation decode logic circuit for controlling access to each register_latch bank, said operation decode logic having a Register_Select output node for selecting a specific one of said register_latch banks, a Write_Valid output node for issuing a Write_Valid signal during a valid write operation, and a Read_Valid output node for issuing a Read_Valid signal during a valid read operation;
• wherein each register_latch bank includes:
• a data input node coupled to a predetermined data line on said data bus;
• a data output node coupled to said predetermined data line on said data bus;
• a Register_Select input node coupled to said Register_Select output node;
• a Write_Select input node responsive to said Write_Select output;
• a Write_Valid input node responsive to said Write_Valid signal;
• a Read_Select input node responsive to said Read_Select output;
• a Read_Valid input node responsive to said Read_Valid signal;
• wherein said Write_Select input node is effective for selectively placing said register_latch bank in a write mode of operation in response to said Write_Valid signal being issued, and said register latch bank disregards said Write_Select input if said Write_Valid signal is not issued;
• and
• wherein said Read_Select input node is effective for placing said register_latch bank in a read mode of operation in response to said Read_Valid signal being issued, and said register_latch bank disregards said Read_Select input node if said Read_Valid signal is not issued.