Performance of a data processing apparatus

Abstract

Techniques for improving the performance of a data processing apparatus are disclosed. The data processing apparatus is operable to execute a data access instruction which causes a first plurality of data items to be transferred between registers and memory. The data processing apparatus is also operable to transfer a second plurality of data items between the registers and the memory in each processing cycle. The data processing apparatus comprises: decode logic operable in response to receipt of one of the data access instruction to determine a number of reserved processing cycles to be reserved for the execution of the data access instruction, the number of reserved processing cycles being determined to be a number of processing cycles which would enable greater than the first plurality of data items to be transferred in those reserved processing cycles. Hence, a greater number of processing cycles are reserved than are strictly necessary. Whilst it will be appreciated that this may have a slight performance impact on data access instructions which take the minimum possible time to execute, reserving more processing cycles than should be necessary helps to ensure that for those data access instructions which take longer to execute, a replay mechanism is unlikely to need to be invoked. It has been found that such an approach can significantly improve the performance of the data processing apparatus.

Dependencies are inferred from the claim text.