Embedded IC test circuits and methods
AssigneeUniversity of Florida Research Foundation, Inc.
InventorsWilliam Eisenstadt, Robert Fox, Jang Yoon, Tao Zhang
Life of this patent
Estimating the term…
Abstract
A self-testing transceiver having an on-chip power detection capability is provided. The self-testing transceiver can include a semiconductor substrate and a transmitter having a high-power amplifier disposed on the substrate. The self-testing transceiver also can include a receiver disposed on the substrate for selectively coupling to an antenna. The self-testing transceiver can further include at least one power detector disposed on the semiconductor substrate for determining a power such as an RMS and/or peak-power of a signal at an internal node of the self-testing transceiver. Additionally, the self-testing transceiver can include a loopback circuit disposed on the substrate.
Claims27
A self-testing transceiver having an on-chip power detection capability, the self-testing transceiver comprising:
- a semiconductor substrate;
- a transmitter disposed on said substrate and comprising a high-power amplifier;
- a receiver disposed on said substrate for selectively coupling to an antenna;
- at least one power detector disposed on said semiconductor substrate for determining a power of a signal at an internal node of the self-testing transceiver;
- and
- a loopback circuit disposed on said substrate, said loopback circuit comprising an attenuator, a preamplifier, a first switch for switching said preamplifier between said attenuator and said high-power amplifier, a low-noise amplifier, and a second switch for switching said low-noise amplifier between said attenuator and said antenna;
- wherein in a self-testing mode said first switch connects said preamplifier to said attenuator and said second switch connects said attenuator to said low-noise amplifier to thereby provide a signal path for a test signal from said preamplifier to said low-noise amplifier through said attenuator.
An on-chip loopback circuit operable at frequencies of at least 100 MHz for testing a transmitter, receiver, or transceiver, the testing circuit comprising:
- a semiconductor substrate;
- a signal attenuator disposed on said semiconductor substrate;
- a first switch disposed on said semiconductor for switching a transmitter preamplifier between said attenuator and a high-power amplifier;
- and
- a second switch disposed on said semiconductor for switching a low-noise amplifier between said attenuator and an antenna;
- wherein in a self-testing mode said first switch connects said attenuator to the preamplifier and said second switch connects said attenuator to the low-noise amplifier to provide a signal path for a test signal from the preamplifier to the low-noise amplifier through said attenuator.
A power detector, comprising:
- an initial-stage attenuator for attenuating a received signal, said initial-stage attenuator having a signal input and a signal output;
- a final-stage attenuator electrically connected to said initial-stage attenuator for also attenuating the received signal, said final-stage attenuator having a signal input and a signal output;
- at least one intermediate-stage attenuator connected in series between said initial-stage attenuator and said final-stage attenuator for also attenuating the received signal;
- an initial-stage detection unit connected to said signal input of said initial-stage attenuator for providing a first power measurement;
- an intermediate-stage detection unit connected to said signal output of said initial-stage attenuator for providing a second power measurement;
- at least one additional intermediate-stage detection unit connected to said signal input of said final-stage attenuator for providing a third power measurement;
- a final-stage detection unit connected to said signal output of said final-stage attenuator;
- and
- a determining module connected to each of said detection units for determining a power measurement of the received signal.
Dependencies are inferred from the claim text.