Integrated circuit fabrication

A method of making a plurality of conductive lines in an array, the method comprising:

• providing a film stack including a substrate in contact with a plurality of conductive plugs, an insulating film overlying the conductive plugs, a lower mask layer overlying the insulating film, and an array of spacers formed over the lower mask layer;
• depositing a sacrificial film over the lower mask layer and the array of spacers;
• forming a resist mask over a portion of the sacrificial film, the resist mask defining an opening over the array of spacers, wherein the lower mask layer and the sacrificial film can be etched selectively with respect to the resist mask;
• etching the sacrificial film and exposing a portion of the lower mask layer;
• etching the lower mask layer and exposing a portion of the insulating film;
• etching a plurality of trenches in the exposed portion of the insulating film to expose at least a portion of the conductive plugs;
• performing a metal deposition into the plurality of trenches;
• and
• forming a planar surface alternating between the metal and the insulating film in a damascene process.

A method of pitch multiplication for damascene features in an integrated circuit, the method comprising:

• providing a substrate;
• performing a first masking process to define an array of spacer lines over the substrate, the spacer lines separated by a plurality of gaps;
• performing a second masking process that blocks a portion of the spacer lines and that defines a plurality of interconnects in a logic region of the integrated circuit;
• etching a plurality of trenches in the gaps between the spacer lines except in the blocked portion;
• depositing a metal layer to form a plurality of metal lines in the trenches;
• and
• providing a planar surface on the metal layer to isolate the metal lines in the trenches.

A method of forming integrated circuit components on a substrate, the method comprising:

• using a lithographic technique to pattern a first resist layer and define a plurality of lines;
• using a pitch multiplication technique to form a pattern of spacers around a region defined by the plurality of lines, wherein the spacers comprise elongate loops having loop ends;
• depositing a second resist layer over the loop ends to define a blocked region of the substrate;
• and
• selectively etching through the spacers to from a plurality of trenches in the substrate without etching in the blocked regions.

A method of forming a memory device that includes an array region and a peripheral region, the method comprising:

• defining a plurality of patterned mask loops in the array region, the patterned mask loops being separated from each other by a gap region;
• overlying a lithographic mask over a portion of the array region and at least a portion of a peripheral region, wherein the lithographic mask covers at least a portion of the patterned mask loops;
• forming a conductive material in a region left exposed by the lithographic mask;
• and
• forming a plurality of contacts over the conductive material, wherein at least one of the plurality of contacts is positioned within the patterned mask loops, and wherein at least one of the plurality of contacts is positioned in the gap region separating the patterned mask loops.