Integrated circuit fabrication

A method of defining an interconnect pattern in an integrated circuit, the method comprising:

• designing a plurality of pitch multiplied closed spacer loops that do not overlap each other, wherein
• the lithography technique is capable of resolving spacer loops having a minimum feature size F,
• the plurality of spacer loops have a loop width xF that is substantially constant, with x defining a pitch multiplication scaling constant corresponding to a feature size of the spacer loops, and
• the spacer loops are separated from each other by a variable gap distance, the minimum gap distance being (1−x)F;
• and
• define a pattern of metal interconnects to be formed in a damascene process, wherein the pattern of metal interconnects configured to connect to the gaps separating the spacer loops, wherein
• the metal interconnects have a minimum width (1−x)F if separated from a spacer loop on two sides, have a minimum width ((1−x)F+D) if separated from a spacer loop on one side, and have a minimum width F if spatially unrestricted by a spacer loop, with D defining a maximum misalignment between the spacer loops and the metal interconnects, and
• the metal interconnects are separated from each other by a minimum spacing of xF if separated by a spacer and of F if not separated by a spacer.

A masking process comprising:

• providing a substrate;
• defining a first pattern over a first region of the substrate using a pitch multiplication technique, the first pattern including at least one pair of features connected by a looped end connection;
• defining a second pattern over a second region of the substrate;
• and
• defining a derivative pattern of the first pattern, wherein a pair of features corresponding to the at least one pair of features are not connected by the looped end connection;
• wherein the first pattern, the second pattern, and the derivative pattern are defined by two masks.