Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry

A method of forming trench isolation in the fabrication of integrated circuitry, comprising:

• forming an isolation trench into semiconductive, material of a semiconductor substrate;
• depositing a spin-on-dielectric to within the isolation trench, the spin-on-dielectric comprising a polysilazane;
• etching the polysilazane effective to recess the spin-on-dielectric in the isolation trench relative to an outermost surface of the semiconductive material adjacent the isolation trench, the etching comprising exposure to an etching fluid comprising at least one of a) an aqueous fluid having a pH greater than 7.0, or b) a basic fluid solution;
• and
• after the etching, annealing remaining spin-on-dielectric comprising polysilazane within the isolation trench effective to form a trench isolation dielectric within the isolation trench which is different in composition from the spin-on-dielectric.

A method of fabricating integrated circuitry, comprising:

• depositing a spin-on-dielectric over a semiconductor substrate, the spin-on-dielectric comprising a polysilazane;
• etching only some of the polysilazane from the semiconductor substrate, the etching comprising exposure to an etching fluid comprising at least one of a) an aqueous fluid having a pH greater than 7.0, or b) a basic fluid solution;
• and
• after the etching, annealing remaining spin-on-dielectric comprising polysilazane effective to form an annealed dielectric which is different in composition from the spin-on-dielectric.