Power semiconductor device having buried gate bus and process for fabricating the same
AssigneePyramis Corporation
InventorsJun Zeng, Po-I Sun
Life of this patent
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Abstract
A power semiconductor device includes a substrate, a gate oxide layer, a gate bus layer, an inter-layer dielectric layer and a metal bus layer. The substrate has a trench structure therein. The gate oxide layer is formed on surfaces of the substrate and the trench structure. The gate bus layer is formed on the gate oxide layer inside the trench structure. The inter-layer dielectric layer is formed on the gate oxide layer and a portion of the gate bus layer, thereby defining a contact window. The metal bus layer is formed on the inter-layer dielectric layer and the trench structure, and connected to the gate bus layer via the contact window.
Claims19
A power semiconductor device having a buried gate bus, comprising:
- a substrate having a trench structure therein;
- a gate oxide layer formed on surfaces of said substrate and said trench structure;
- a gate bus layer formed on said gate oxide layer inside said trench structure;
- an inter-layer dielectric layer formed on said gate oxide layer and a portion of said gate bus layer, thereby defining a contact window;
- and
- a metal bus layer formed on said inter-layer dielectric layer and said trench structure, and connected to said gate bus layer via said contact window.
A process for fabricating a power semiconductor device having a buried gate bus, comprising steps of:
- (a) providing a substrate;
- (b) etching said substrate to form a trench structure in said substrate;.
- (c) forming a gate oxide layer on the surfaces of said substrate and said trench structure;
- (d) depositing a polysilicon layer on said gate oxide layer;
- (e) etching said polysilicon layer to form a gate bus layer on said gate oxide layer inside said trench structure;
- (f) forming an inter-layer dielectric layer on said gate oxide layer and a portion of said gate bus layer, thereby defining a contact window;
- and
- (g) forming a metal bus layer on aid inter-layer dielectric layer and said trench structure, and connecting said metal bus layer to said gate bus layer via said contact window.
A power semiconductor device having a buried gate bus, comprising:
- a substrate having a trench structure therein;
- a gate bus layer formed on internal walls of said trench structure;
- an inter-layer dielectric layer formed on said substrate and a portion of said gate bus layer, thereby defining a contact window;
- and
- a metal bus layer formed on said inter-layer dielectric layer and said trench structure, and connected to said gate bus layer via said contact window.
Dependencies are inferred from the claim text.