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US 2006/0216885 A1Published application
Method for fabricating semiconductor device
AssigneeHynix Semiconductor Inc.
InventorSang Lee
Life of this patent
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Abstract
Disclosed herein is a method for fabricating a memory device. According to the present invention, during an etching process for forming a recess gate region, a device isolation film is etched using a mask partially exposing a channel region and its neighboring device isolation film, and then a semiconductor substrate is etched, thus preventing a silicon horn in the recess gate region from being formed. Accordingly, a margin for the etching process is increased.
Claims11
A method for fabricating a semiconductor device, comprising the steps of:
- (a) forming a device isolation film defining an active region by performing a STI process on a pad insulating film formed on a semiconductor substrate;
- (b) forming a polysilicon layer on an entire surface of the semiconductor device;
- (c) defining an island-type recess region passing across the active region, and then etching the polysilicon layer, the pad insulating film and the device isolation film by a predetermined thickness in the island-type recess region to form a recess exposing both sidewalls of the active region, wherein a width of the island-type recess region is smaller than a line width of a gate region in a longitudinal direction of the active region and a width of the island-type recess region is lager than a line width of the active region in a longitudinal direction of the gate region;
- (d) etching the semiconductor substrate within the recess using the remaining polysilicon layer as an etching mask to form a recess gate region, wherein the polysilicon layer and the semiconductor substrate are simultaneously etched;
- (e) removing the pad insulating film by a predetermined thickness, and then forming a gate oxide film on the active region;
- (f) forming a lower gate conductive layer filling up the recess gate region on the entire surface of the semiconductor device and sequentially forming a upper gate conductive layer and a hard mask layer on the lower gate conductive layer;
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- (g) selectively etching the hard mask layer, the upper gate conductive layer and the lower gate conductive layer using a gate mask to form a gate structure.
5 more elements
Dependencies are inferred from the claim text.