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US 2006/0216870 A1Published application
High density SRAM cell with latched vertical transistors
OwnerWendell Noble, Leonard Forbesinventors
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Abstract
High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.
Claims13
1-52. (canceled)
A method of forming a memory cell for storing information as one of at least two stable current states, comprising:
- providing a semiconductor substrate;
- forming a multi-region vertical thyristor comprising at least four doped silicon regions;
- forming at least two polysilicon gates spanning at least two respective junctions of said multi-region vertical thyristor;
- and
- connecting said at least two polysilicon gates to voltage source conductors capable of receiving a voltage to produce latch-up in said multi-region vertical thyristor.
2 more elements
Dependencies are inferred from the claim text.