Wafer-level package for integrated circuits
AssigneeMemsic, Inc.
InventorYang Zhao
Life of this patent
Estimating the term…
Abstract
A wafer-level packaged IC is made by attaching a cap wafer to the top of an IC wafer before cutting the IC wafer, i.e. before singulating the plurality of die on the IC wafer. The cap wafer is mechanically attached and electrically connected to the IC wafer, then the die are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the top surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without die) can be stacked to form a “multi-story” IC.
Claims75
A method of wafer-level packaging an integrated circuit (IC) die, comprising:
- providing an IC wafer comprising a plurality of die and at least one electrical contact point associated with each die;
- providing a first semiconductor cap wafer;
- forming electrically conductive paths through the first semiconductor cap wafer at positions corresponding to respective ones of the electrical contact points on the IC wafer, such that each electrically conductive path extends from a first side of the first semiconductor cap wafer to a second side of the first semiconductor cap wafer and is insulated from at least a portion of the first semiconductor cap wafer;
- and
- before cutting the die from the IC wafer, attaching the first semiconductor cap wafer to the IC wafer, such that the ends of the conductive paths on the first side of the first semiconductor cap wafer are electrically connected to the respective electrical contact points on the IC wafer.
A composite wafer, comprising:
- at least a portion of an IC wafer comprising a plurality of die and at least one electrical contact point associated with each die;
- at least a portion of a first semiconductor cap wafer, a first side of which is rigidly attached to one side of the at least a portion of the IC wafer, wherein the at least a portion of the first semiconductor cap wafer overlays at least some of the plurality of die on the at least a portion of the IC wafer, and the at least a portion of the first semiconductor cap wafer includes a plurality of electrically insulated passages therethrough at respective positions corresponding to locations of the electrical contact points on the at least a portion of the IC wafer;
- and
- electrically conductive material filling each insulated passage and extending from the first side of the at least a portion of the first semiconductor cap wafer to a second side thereof;
- and
- for each insulated passage, an electrical connection between the end of the electrically conductive material at the first side of the at least a portion of the first semiconductor cap wafer and the respective electrical contact pad on the at least a portion of the IC wafer.
A wafer-level package, comprising:
- at least a portion of an integrated circuit (IC) wafer including at least one die and a plurality of electrical contact points associated with the die;
- a first semiconductor cap, a first side of which is rigidly attached to one side of the at least a portion of the IC wafer, the first semiconductor cap having a plurality of electrically insulated passages therethrough at respective positions corresponding to locations of the electrical contact points on the at least a portion of the IC wafer;
- electrically conductive material filling each insulated passage and extending from the first side of the first semiconductor cap to a second side of the first semiconductor cap;
- and
- for each insulated passage, an electrical connection between the end of the electrically conductive material at the first side of the first semiconductor cap and the respective electrical contact point on the at least a portion of the IC wafer.
Dependencies are inferred from the claim text.