Code conversion circuit

Abstract

A code conversion circuit is disclosed that converts a NRZ data signal into another NRZ data signal. The code conversion circuit includes a demultiplexer to demultiplex a NRZ data signal into plural parallel data signals, a conversion circuit to receive the demultiplexed parallel data signals, and a multiplexer to multiplex plural data signals output from the conversion circuit. The conversion circuit includes a first exclusive OR circuit to calculate logical exclusive OR of a first data signal of the parallel data signals and a second data signal of parallel data signals that is delayed by one bit by a delay circuit, an AND circuit to calculate logical AND of an output signal representing the logical exclusive OR calculated by the first exclusive OR circuit and a clock signal corresponding to a transmission speed of the parallel data signals, a T flip-flop to receive an output signal representing the logical AND calculated by the AND circuit, and a second exclusive OR circuit to calculate logical exclusive OR of a NRZ data signal output from the T flip-flop and the second data signal.

Dependencies are inferred from the claim text.