Communication data controller
AssigneeFujitsu Limited
InventorKazuo Aoki
Life of this patent
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Abstract
A communication data controller is provided which is capable of correctly retransmitting transmission data even if a block of the transmission data exceeding a FIFO (First-In First-Out) memory is written in an overwriting manner to the FIFO memory. The memory stores transmission data to be transmitted to a communication device. Transmission data stored in the memory is written and read to and from the FIFO memory by a CPU (Central Processing Unit). A DMAC (Direct Memory Access Controller) driver, when a request for retransmission of a block is made in the case where the block of transmission data exceeding a capacity of the FIFO memory is written to the FIFO memory, drives the DMAC and transfers the block being stored in the memory to the communication data controller.
Claims9
A communication data controller for controlling communication of transmission data being stored in a memory connected through a bus, comprising:
- a FIFO (First-In First-Out) memory to which the transmission data is written and from which the transmission data is read out;
- and
- a DMAC (Direct Memory Access Controller) driver which, when a block of the transmission data exceeding a capacity of the FIFO memory is written to said FIFO memory, if a request for retransmission of the transmission data is made, drives said DMAC being connected to said bus and transfers the block of the transmission data stored in said memory to said FIFO memory.
A communication data controller for controlling communication of communication data comprising:
- a FIFO memory to which transmission data to which retransmission starting point information informing that the point is a starting point for retransmission has been attached is written and from which the transmission data is read out;
- a read pointer to generate a reading address used to read the transmission data from said FIFO memory;
- a reload pointer to output a reading address being stored therein to said read pointer when a request for retransmission of the transmission data is made;
- and
- a pointer controller to store the reading address generated by said read pointer in said reload pointer according to the retransmission starting point information for the transmission data read out from said FIFO memory.
A communication data controller for controlling communication of transmission data stored in a memory connected through a bus comprising:
- a FIFO memory to which transmission data to which retransmission starting point information informing that the point is a starting point for retransmission has been attached is written and from which the transmission data is read out;
- a read pointer to generate a reading address used to read the transmission data from said FIFO memory;
- a relaod pointer to output the reading address being stored therein to said read pointer when a request for retransmission of the transmission data is made;
- a pointer controller to store the reading address generated by said read pointer in said reload pointer according to the retransmission starting point information for the transmission data read out from said FIFO memory;
- and
- a DMAC driver which, when a block of the transmission data exceeding a capacity of the FIFO memory is written to said FIFO memory, if a request for retransmission of the transmission data is made, drives said DMAC being connected to said bus and transfers the block of the transmission data stored in said memory to said FIFO memory.
Dependencies are inferred from the claim text.